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參數(shù)資料
| 型號： | AAT1171 |
| 廠商： | Advanced Analog Technology,lnc. |
| 英文描述： | 600mA Voltage-Scaling Step-Down Converter for RF Power Amplifiers with Bypass Switch |
| 中文描述： | 600毫安電壓調(diào)節(jié)射頻功率放大器的旁路開關(guān)降壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AAT1171 |
AAT1171
600mA Voltage-Scaling Step-Down Converter
for RF Power Amplifiers with Bypass Switch
1171.2006.06.1.0
13
DAC Output Voltage Control
The output voltage is programmed by way of the
DAC input voltage. The DAC to output gain for the
AAT1171 is 3.
The DAC input voltage range is 0.2V to 1.2V, which
corresponds to an output voltage range of 0.6V to
3.6V (see Figure 1). For a 1.3V DAC level, the
bypass switch is activated and the output voltage
level is equivalent to the input voltage minus the
bypass MOSFET (R
DS(ON)(bp)
) drop.
Bypass Mode
In bypass mode, the AAT1171 bypasses the output
inductor, connecting the input directly to the output
through a low R
DS(ON)
85m
Ω
MOSFET. Bypass
mode is initiated by applying 1.3V to the DAC input
or by applying a logic high to the bypass input.
When not activated, a logic level low must be
applied to the bypass input pin. The bypass MOS-
FET current is limited to 600mA.
LL/PWM Control
Two control modes are available with the AAT1171:
LL mode and PWM mode. PWM mode maintains a
fixed switching frequency regardless of load. The
fixed switching frequency gives the advantage of
lower output ripple and simplified output and input
noise filtering. PWM mode also provides a faster
output voltage response to changes in the DAC
voltage.
In LL mode, the converter transitions to a variable
switching frequency as the load decreases below
100mA. Above 100mA, where switching losses no
longer dominate, the switching frequency is fixed.
The LL mode's effect on the DAC to output voltage
response time is most notable when transitioning
from a high output voltage to a low voltage. When
the converter is in PWM mode, the inductor current
can be reversed and the output voltage actively
discharged by the synchronous MOSFET. While in
LL mode, the output voltage is discharged by the
load only, resulting in a slower response to a DAC
transition from a high to a low voltage.
For PWM mode, apply a logic level high to the
MODE/SYNC pin; for LL mode, apply a logic level
low to the MODE/SYNC pin.
V
OUT
= 3 · V
DAC
Figure 1: V
OUT
vs. V
DAC
.
1V
2V
3V
4V
3.6V
1V
1.2V
DAC Output
O
0.6V
0.2V
V
IN
1.3V
B
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