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參數(shù)資料
| 型號： | AAT1156_07 |
| 廠商： | Advanced Analog Technology,lnc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1MHz 700mA Step-Down DC-DC Converter |
| 中文描述： | 1MHz的700mA的降壓型DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 586K |
| 代理商： | AAT1156_07 |
AAT1156
1MHz 700mA Step-Down DC-DC Converter
10
1156.2007.01.1.4
the load, output voltage, and input voltage source
impedance characteristics. Values range from 1
μ
F
to 10
μ
F. The input capacitor RMS current varies
with the input voltage and output voltage. The equa-
tion for the RMS current in the input capacitor is:
The input capacitor RMS ripple current reaches a
maximum when V
IN
is two times the output voltage,
where it is approximately one half of the load cur-
rent. Losses associated with the input ceramic
capacitor are typically minimal and are not an
issue. Proper placement of the input capacitor is
shown in the reference design layout in Figure 2.
Output Capacitor
Since there are no external compensation compo-
nents, the output capacitor has a strong effect on
loop stability. Larger output capacitance will reduce
the crossover frequency with greater phase margin.
For the 1.5V, 0.7A design using the 3.3
μ
H inductor,
two 22
μ
F capacitors provide a stable output. In
addition to assisting in stability, the output capacitor
limits the output ripple and provides holdup during
large load transitions. The output capacitor RMS
ripple current is given by:
For an X7R or X5R ceramic capacitor, the ESR is
so low that dissipation due to the RMS current of
the capacitor is not a concern. Tantalum capacitors
with sufficiently low ESR to meet output voltage rip-
ple requirements also have an RMS current rating
well beyond that actually seen in this application.
Layout
Figures 2 and 3 display the suggested PCB layout
for the AAT1156. The following guidelines should
be used to help ensure a proper layout.
1. The input capacitor (C1) should connect as
closely as possible to VP (Pins 10, 11, and 12)
and PGND (Pins 1, 2, and 3).
2. C3, C4, and L1 should be connected as closely
as possible. The connection from L1 to the LX
node should be as short as possible.
3. The feedback trace (Pin 4) should be separate
from any power trace and connect as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
4. The resistance of the trace from the load return
to PGND (Pins 1, 2, and 3) should be kept to a
minimum. This will help to minimize any error in
DC regulation due to differences in the potential
of the internal signal ground and the power
ground.
5. Low pass filter R1 and C2 provide a cleaner bias
source for the AAT1156 active circuitry. C2 should
be placed as closely as possible to SGND (Pin 5)
and VCC (Pin 9).
V
OUT
(V
IN
- V
OUT
)
L
F
S
V
IN
1
I
RMS
=
2
3
V
O
V
O
V
IN
V
IN
I
RMS
= I
O
1 -
Figure 2: AAT1156 Evaluation
Board Top Side.
Figure 3: AAT1156 Evaluation
Board Bottom Side.
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