參數(shù)資料
型號: A8904SLP
廠商: Allegro MicroSystems, Inc.
英文描述: 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
中文描述: 3相無刷直流電動機(jī)控制器/驅(qū)動器,反電動勢遙感
文件頁數(shù): 7/18頁
文件大?。?/td> 1160K
代理商: A8904SLP
8904
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
www.allegromicro.com
7
Terminal Functions
A8904SLB
(SOIC)
1
2
A8904SLP
(HTSSOP)
15
16
Terminal Name
LOAD SUPPLY
C
D2
Function
V
BB
; the 5 V or 12 V motor supply.
One of two capacitors used to generate the ideal commutation points from
the back-EMF zero crossing points.
Timing capacitor used by the watchdog circuit to blank out the back-EMF
comparators during commutation transients, and to detect incorrect motor
position.
Startup oscillator timing capacitor.
No( internal) connection.
Power amplifier A output to motor.
No (internal) connection.
Power and logic ground and thermal heat sink.
Power ground.
No (internal) connection.
Power amplifier B output to motor.
Power amplifier C output to motor.
Motor centertap connection for back-EMF detection circuitry.
Active low turns ON all three sink drivers shorting the motor windings to
ground. External capacitor and resistor at B
RAKE
provide brake delay.
The brake function can also be controlled via the serial port.
External reservoir capacitor used to hold charge to drive the source drivers’
gates. Also provides power for brake circuit.
Analog ground.
Analog voltage input/output to control motor current. Also, compensation node
for internal speed control loop.
External tachometer input. Can use sector or index pulses from disk to
provide precise motor speed feedback to internal frequency-locked loop.
V
DD
; the 5 V logic supply.
Clock input for the speed reference counter.
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in
real time, controlled by 2-bit multiplexer via serial port.
No (internal) connection.
Power and logic ground and thermal heat sink.
Logic ground.
When pulled low forces the chip into sleep mode; clears all serial port bits.
No (internal) connection.
Strobe input (active low) for data word.
Clock input for serial port.
Sequential data input for the serial port.
One of two capacitors used to generate the ideal commutation points from
the back-EMF zero crossing points.
C
WD
3
17
C
ST
NC
OUT
A
NC
GROUND
POWER GROUND
NC
OUT
B
OUT
C
CENTERTAP
4
5
18
19
20
21
22*
23
24
25
26
27
6-7
8
9
10
11
BRAKE
C
RES
12
28
ANALOG GROUND
FILTER
1*
13
14
2
3
SECTOR DATA
LOGIC SUPPLY
OSCILLATOR
DATA OUT
15
16
17
4
5
6
NC
7
8*
9
10
11
12
13
14
GROUND
DIGITAL GROUND
18-19
20
21
22
23
24
RESET
NC
CHIP SELECT
CLOCK
DATA IN
C
D1
* For the A8904SLP, ground terminals 1, 8, and 22 must be connected together externally.
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