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參數(shù)資料
| 型號(hào)： | A83516L-40 |
| 廠商： | AMIC Technology Corporation |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 8 Bit Microcontroller |
| 中文描述： | 8位微控制器 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 270K |
| 代理商： | A83516L-40 |
A83516 Series
PRELIMINARY
(November, 1998, Version 0.0)
6
AMIC Technology, Inc.
AC Characteristics
(T
A
= -25
°
C to + 85
°
C, VCC = 5V
±
10%)
Symbol
Parameter
Min.
Max.
Unit
Program Memory Cycle
t
AP
ALE Pulse Width
2t
ck
– 20
1
-
ns
t
ALS
Address Valid to ALE Low
1t
ck
-
ns
t
ALH
Address Hold from ALE Low
1t
ck
-
ns
t
op
PSEN
Pulse Width
3t
ck
- 20
1
-
ns
t
AO
ALE Low to
PSEN
Low
1t
ck
-
ns
t
OI
2
PSEN
Low to Valid Instruction in
-
2t
ck
ns
t
IDO
Input Instruction Hold after
PSEN
High
-
1t
ck
ns
t
IFO
Input Instruction Float after
PSEN
High
-
1t
ck
ns
External Clock
f
OPER
Clock Frequency
0
40
MH
Z
t
CK
3
Clock Period
25
-
ns
t
CKH
4
Clock High Time
10
-
ns
t
CKL
4
Clock Low Time
10
-
ns
Data Memory Cycle
t
PR
RD
Pulse Width
6t
ck
- 20
1
-
ns
t
PD
RD
Low to Valid Data in
-
4t
ck
ns
t
DHR
Data Hold from
RD
High
0
2t
ck
ns
t
DFR
Data Float from
RD
High
0
2t
ck
ns
t
AR
ALE Low to
RD
Low
3t
ck
3t
ck
+ 20
1
ns
t
WP
WR
Pulse Width
6t
ck
- 20
1
-
ns
t
DS
Valid Data to
WR
Low
1t
ck
-
ns
t
DHW
Data Hold from
WR
High
1t
ck
-
ns
t
AW
ALE Low to
WR
Low
3t
ck
3t
ck
+ 20
1
ns
Serial Port Cycle
t
SCK
Serial Port Clock
12t
ck
-
ns
t
KI
Clock Rising Edge to Valid Input Data
-
11t
ck
ns
t
IKH
Input Data to Serial Clock Rising Clock Hold Time
0
-
ns
t
OKS
Output Data to Serial Clock Rising Edge Setup Time
11t
ck
-
ns
t
OKH
Output Data to Serial Clock Rising Edge Hold Time
1t
ck
-
ns
1. This 20 ns is due to buffer driving delay and wire loading.
2. Instruction cycle time is 12 t
ck.
3. tck = 1/ f
oper
4. There are no duty cycle requirements on the XTAL1 input.
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