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參數(shù)資料
| 型號： | A6B595KLWTR-T |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 0.5 A LATCH BASED PRPHL DRVR, PDSO20 |
| 封裝： | LEAD FREE, PLASTIC, MS-013AC, SOICW-20 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 337K |
| 代理商： | A6B595KLWTR-T |
8-Bit Serial-Input DMOS Power Driver
A6B595
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 20 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CLK) ............................................. 40 ns
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) ............................................... 50 ns
w(OE) ................................ 4.5 μs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift reg-
ister on the rising edge of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
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