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參數(shù)資料
| 型號(hào)： | A6810KLWTR |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | VACUUM FLUOR DISPLAY DRIVER, PDSO20 |
| 封裝： | MS-013AC, SOIC-20 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 322K |
| 代理商： | A6810KLWTR |
10-Bit Serial Input Latched Source Driver
A6810
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the PNP active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
BLANKING
OUT
N
Dwg. WP-030A
DATA
10%
50%
en(BQ)
t
dis(BQ)
t
HIGH = ALL OUTPUTS BLANKED (DISABLED)
r
t
f
t
50%
90%
A.
Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................... 25 ns
B.
Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................................ 25 ns
C.
Clock Pulse Width, tw(CH) ................................................. 50 ns
D.
Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns
E.
Strobe Pulse Width, tw(STH) .............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable; operation at high temperatures will
reduce the specied maximum clock frequency.
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
OUT
N
Dwg. WP-029
50%
SERIAL
DATA OUT
DATA
10%
90%
50%
C
A
B
D
E
LOW = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
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| A6810KLWTR-T | 功能描述:IC SOURCE DRVR 10BIT SER 20SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 內(nèi)部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:高端/低端驅(qū)動(dòng)器 輸入類型:SPI 輸出數(shù):8 導(dǎo)通狀態(tài)電阻:850 毫歐，1.6 歐姆 電流 - 輸出 / 通道:205mA，410mA 電流 - 峰值輸出:500mA，1A 電源電壓:9 V ~ 16 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:PG-DSO-20-45 包裝:帶卷 (TR) |
| A6810SA | 功能描述:IC SOURCE DRVR 10BIT SER 18-DIP RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 內(nèi)部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:高端/低端驅(qū)動(dòng)器 輸入類型:SPI 輸出數(shù):8 導(dǎo)通狀態(tài)電阻:850 毫歐，1.6 歐姆 電流 - 輸出 / 通道:205mA，410mA 電流 - 峰值輸出:500mA，1A 電源電壓:9 V ~ 16 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:PG-DSO-20-45 包裝:帶卷 (TR) |
| A6810SA-T | 功能描述:IC SOURCE DRVR 10BIT SER 18-DIP RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 內(nèi)部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:高端/低端驅(qū)動(dòng)器 輸入類型:SPI 輸出數(shù):8 導(dǎo)通狀態(tài)電阻:850 毫歐，1.6 歐姆 電流 - 輸出 / 通道:205mA，410mA 電流 - 峰值輸出:500mA，1A 電源電壓:9 V ~ 16 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:PG-DSO-20-45 包裝:帶卷 (TR) |
| A6810SA-T | 制造商:Allegro MicroSystems 功能描述:Driver IC Output Current Max:15mA |
| A6810SEP | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS |
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