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參數(shù)資料
| 型號： | A67L16181 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| 中文描述： | 2米x 18，100萬米鼠36 LVTTL，流通過ZeBL的SRAM |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 243K |
| 代理商： | A67L16181 |
A67L16181/A67L06361 Series
PRELIMINARY
(February, 2005, Version 0.1)
15
AMIC Technology, Corp.
READ/WRITE Timing
Note :
1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.
3.
CE
represents three signals. When
CE
= 0, it represents
CE
= 0,
CE2
= 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most
recent data may be from the input data register.
A3
A2
A1
A4
A5
D(A1)
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
: Don't Care
: Undefined
1
2
3
4
5
t
KHKH
6
7
8
9
10
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
I/O
COMMAND
A6
A7
D(A2)
D(A2+1)
OE
t
KLKH
t
EVK
H
t
KHE
X
t
KHKL
t
KHCX
t
CVKH
t
KHAX
t
AVKH
t
KHDX
t
DVKH
t
KHQV
t
KHQX1
Q(A3)
t
KHQX
t
GLQX
t
KHQX
t
GHQZ
Q(A6)
D(A5)
Q(A4+1)
t
KHQZ
t
GLQV
Q(A4)
D(A7)
相關PDF資料 |
PDF描述 |
|---|---|
| A67L16181E | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181E-6.5 | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181E-7.5 | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181-8.5 | CAT 6 BLADE SERVER PATCH CABLE 15 WHT |
| A67L06361E | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A67L16181-8.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181E-6.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181E-7.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L1618E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
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