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參數(shù)資料
| 型號： | A67L16181-8.5 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAT 6 BLADE SERVER PATCH CABLE 15 WHT |
| 中文描述： | 2米x 18，100萬米鼠36 LVTTL，流通過ZeBL的SRAM |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 243K |
| 代理商： | A67L16181-8.5 |
A67L16181/A67L06361 Series
PRELIMINARY
(February, 2005, Version 0.1)
6
AMIC Technology, Corp.
Pin Description
Pin No.
Symbol
Description
LQFP (X18)
LQFP (X36)
37
36
35,34,33,32,
100,99,82,81
44,45,46,47,
48,49,50,83,84
43
80
37
36
35,34,33,32,
100,99,82,81
45,46,47,48,
49,50,83,84,43
44
A0
A1
A2 – A9
A11-A19
A20
A10
Synchronous Address Inputs : These inputs are registered and
must meet the setup and hold times around the rising edge of
CLK. Pins 83 and 84 are reserved as address bits for higher-
density 9Mb and 18Mb DBA SRAMs, respectively. A0 and A1 are
the two lest significant bits (LSB) of the address field and set the
internal burst counter if burst is desired.
93 (
BW1
)
94 (
BW2
)
93 (
BW1
)
94 (
BW2
)
95 (
BW3
)
96 (
BW4
)
BW1
BW2
BW3
BW4
Synchronous Byte Write Enables : These active low inputs allow
individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of
CLK. BYTE WRITEs need to be asserted on the same cycle as
the address,
BWs
are associated with addresses and apply to
subsequent data.
BW1
controls I/Oa pins;
BW2
controls I/Ob pins;
BW3
controls I/Oc pins;
BW4
controls I/Od pins.
89
89
CLK
Clock : This signal registers the address, data, chip enables, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
98
98
CE
Synchronous Chip Enable : This active low input is used to enable
the device. This input is sampled only when a new external
address is loaded (ADV/
LD
LOW).
92
92
CE2
Synchronous Chip Enable : This active low input is used to enable
the device and is sampled only when a new external address is
loaded (ADV/
LD
LOW). This input can be used for memory depth
expansion.
97
97
CE2
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/
LD
LOW). This input can be used for
memory depth expansion.
86
86
OE
Output Enable : This active low asynchronous input enables the
data I/O output drivers.
85
85
ADV/
LD
Synchronous Address Advance/Load : When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When HIGH, R/
W
is
ignored. A LOW on this pin permits a new address to be loaded at
CLK rising edge.
87
87
CEN
Synchronous Clock Enable : This active low input permits CLK to
propagate throughout the device. When HIGH, the device ignores
the CLK input and effectively internally extends the previous CLK
cycle. This input must meet setup and hold times around the
rising edge of CLK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A67L06361E | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L06361E-7.5 | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L06361E-8.5 | 2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L0636E-3.2 | 2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
| A67L1618E-2.6 | GIGABASE 350 CAT5E PATCH 3 FT, SNAGLESS, WHITE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A67L16181E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181E-6.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L16181E-7.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Flow-through ZeBL SRAM |
| A67L1618E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
| A67L1618E-2.6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM |
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