參數(shù)資料
型號(hào)： A65H83181SERIES
廠商： AMIC Technology Corporation
英文描述： 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output
中文描述： 128K的× 36
文件頁數(shù)： 6/21頁
文件大?。?/td> 530K
代理商： A65H83181SERIES
A65H73361/A65H83181 Series
PRELIMINARY
(February, 1999, Version 2.0)
5
AMIC Technology, Inc.
Absolute Maximum Ratings*
Power Supply Voltage(V
DD
) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except V
DD
(V
IN
,
V
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Power Dissipation (P
D
) . . . . . . . . .. . . . . . . . . . .. . .1.0W
Operating Temperature (Topr). . . . . . . . .. . 0
°
C to 70
°
C
Storage Temperature (Tbias) . . . . . . .. .. . -10
°
C to 85
°
C
Storage Temperature(Tstg). . . . . . . . . . .-55
°
C to 125
°
C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure the absolute maximum
rating conditions for extended periods may affect device
reliability.
Recommended DC Operating Conditions
(T
J
= 0 to 110
°
C
)
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
Supply Voltage
V
DD
3.15
3.3
3.47
V
1
Output Driver Supply Voltage
V
DDQ
1.4
1.5
1.6
V
1
Input High Voltage
V
IH
V
REF
+0.1
-
V
DDQ
+0.3
V
1, 2
Input Low Voltage
V
IL
-0.3
-
V
REF
-0.1
V
1, 3
Input reference Voltage
V
REF
0.68
0.75
0.90
V
1, 6
Clocks Signal Voltage
V
IN-CLK
-0.3
-
V
DDQ
+0.3
V
1, 4
Differential Clocks Signal Voltage
V
DIF-CLK
0.1
-
V
DDQ
+0.6
V
1, 5
Clocks Common Mode Voltage
V
CM-CLK
0.55
-
0.90
V
1
Output Current
I
OUT
-
5
8
mA
1.All voltage reference to V
SS.
All V
DD
V
DDQ
and V
SS
pins must be connected.
2.V
IH
(Max)DC = V
DD
+ 0.3V, V
IH
(Max)AC = V
DD
+ 1.5V (pulse width
≤
4.0ns).
3.V
IL
(Min)DC = -0.3V, V
IL
(Min)AC = -1.5 V (pulse width
≤
4.0ns).
4.V
IN-CLK
specifies the maximum allowable DC excursions of each differential clock (
CK
,
CK
).
5.V
DIF-CLK
specifies the minimum clock differential voltage required for switching.
6.Peak to Peak AC component superimposed on V
REF
may not exceed 5% of V
REF
.
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A65H73361 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output
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