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參數資料
| 型號： | A63L06361E-6.5 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 100萬米鼠36位同步計數器高的Burst SRAM的速度和流量，通過數據輸出 |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 263K |
| 代理商： | A63L06361E-6.5 |
A63L06361
PRELIMINARY (March, 2005, Version 0.1)
10
AMIC Technology, Corp.
Notes:
1. All voltages refer to GND.
2. Overshoot: V
IH
≤
+2V for t
≤
t
KC
/2.
Undershoot: V
IL
≥
-0.7V for t
≤
t
KC
/2.
Power-up:
V
IH
≤
+2 and VCC
≤
1.7V
for t
≤
200ms
3. I
CC1
is given with no output current. I
CC1
increases with greater output loading and faster cycle times.
4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, C
L
= 5pF, as shown in Figure 2. Transition is measured
±
150mV from steady state voltage.
6. At any given temperature and voltage condition, t
KQHZ
is less than t
KQLZ
and t
OEHZ
is less than t
QELZ
.
7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
8.
OE has no effect when a Byte Write enable is sampled LOW.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
10. The load used for V
OH
, V
OL
testing is shown in Figure 2. AC load current is higher than the given DC values.
AC I/O curves are available upon request.
11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10
μ
A.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
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| A63L0636E-3.2F | 1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| A63L06361E-7.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L06361E-7.5F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L06361E-8 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L06361E-8F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L0636E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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