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參數(shù)資料
| 型號： | A62S8308X-70SI |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | TV 13C 13#22D PIN RECP |
| 中文描述： | 256K × 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 278K |
| 代理商： | A62S8308X-70SI |
A62S8308 Series
PRELIMINARY
(March, 2001, Version 0.2)
5
AMIC Technology, Inc.
AC Characteristics
(T
A
= 0
°
C to + 70
°
C or -25
°
C to 85
°
C, VCC = 2.7V to 3.6V)
Symbol
Parameter
A62S8308-55S/SI
(VCC = 3.0V to 3.6V)
A62S8308-70S/SI
(VCC = 2.7V to 3.6V)
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
-
70
-
ns
t
AA
Address Access Time
-
55
-
70
ns
t
ACE1
Chip Enable Access Time
CE1
-
55
-
70
ns
t
ACE2
CE2
-
55
-
70
ns
t
OE
Output Enable to Output Valid
-
30
-
35
ns
t
CLZ1
Chip Enable to Output in Low Z
CE1
10
-
10
-
ns
t
CLZ2
CE2
10
-
10
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
5
-
ns
t
CHZ1
Chip Disable to Output in High Z
CE1
0
20
0
25
ns
t
CHZ2
CE2
0
20
0
25
ns
t
OHZ
Output Disable to Output in High Z
0
20
0
25
ns
t
OH
Output Hold from Address Change
5
-
10
-
ns
Read Cycle
t
WC
Write Cycle Time
55
-
70
-
ns
t
CW
Chip Enable to End of Write
50
-
60
-
ns
t
AS
Address Setup Time
0
-
0
-
ns
t
AW
Address Valid to End of Write
50
-
60
-
ns
t
WP
Write Pulse Width
40
-
50
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
0
25
0
25
ns
t
DW
Data to Write Time Overlap
25
-
30
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
5
-
5
-
ns
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
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相關代理商/技術參數(shù) |
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| A62S8316 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16 BIT LOW VOLTAGE CMOS SRAM |
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| A62S8316V-70SI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16 BIT LOW VOLTAGE CMOS SRAM |
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