參數(shù)資料
型號： A62L256V-70LLU
廠商： AMIC Technology Corporation
英文描述： 32K X 8 BIT LOW VOLTAGE CMOS SRAM
中文描述： 32K的× 8位低電壓CMOS的SRAM
文件頁數(shù)： 10/14頁
文件大小： 146K
代理商： A62L256V-70LLU
A62L256 Series
PRELIMINARY (November, 2001, Version 1.4)
10
AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels
0V, VCC
Input Rise And Fall Time
5 ns
Input and Output Timing Reference Levels
VCC/2
Output Load
See Figure 1
30pF
* Including scope and jig.
C
L
Figure 1. Output Load
Data Retention Characteristics
(T
A
= 0
°
C to 70
°
C or -40oC to +85oC)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
V
DR
VCC for Data Retention
2.0
-
3.6
V
CE
≥
VCC - 0.2V
LL-version
-
0.02
0.5
I
CCDR
Data Retention Current
LLU-version
-
0.02
2
μ
A
VCC = 2V,
CE
≥
VCC - 0.2V
V
IN
≥
0V
t
CDR
Chip Disable to Data Retention Time
0
-
ns
See Retention Waveform
t
R
Operation Recovery Time
t
RC
-
ns
Typical values are measured at T
A
= 25
°
C.
Low VCC Data Retention Waveform
VCC
t
CDR
V
IH
3.0V
t
R
V
IH
3.0V
DATA RETENTION MODE
VCC
≥
2.0V
CE
≥
VCC - 0.2V
CE
相關(guān)PDF資料
PDF描述
A62L256 ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
A62L256-55LL 32K X 8 BIT LOW VOLTAGE CMOS SRAM
A62L256-55LLU 32K X 8 BIT LOW VOLTAGE CMOS SRAM
A62L256-70LL 32K X 8 BIT LOW VOLTAGE CMOS SRAM
A62L256-70LLU ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
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