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參數(shù)資料
| 型號： | A62L256R-70LL |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 32K的× 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 146K |
| 代理商： | A62L256R-70LL |
A62L256 Series
PRELIMINARY (November, 2001, Version 1.4)
6
AMIC Technology, Inc.
AC Characteristics
(T
A
= 0
°
C to +70
°
C or -40oC to +85oC)
Symbol
Parameter
A62L256-55LL/LLU
(VCC = 3.0V to 3.6V)
A62L256-70LL/LLU
(VCC = 2.7V to 3.6V)
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
-
70
-
ns
t
AA
Address Access Time
-
55
-
70
ns
t
ACE
Chip Enable Access Time
-
55
-
70
ns
t
OE
Output Enable to Output Valid
-
30
-
35
ns
t
CLZ
Chip Enable to Output in Low Z
10
-
10
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
5
-
ns
t
CHZ
Chip Disable to Output in High Z
-
20
-
25
ns
t
OHZ
Output Disable to Output in High Z
-
20
-
25
ns
t
OH
Output Hold from Address Change
5
-
10
-
ns
Write Cycle
t
WC
Write Cycle Time
55
-
70
-
ns
t
CW
Chip Enable to End of Write
50
-
60
-
ns
t
AS
Address Set up Time
0
-
0
-
ns
t
AW
Address Valid to End of Write
50
-
60
-
ns
t
WP
Write Pulse Width
40
-
50
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
-
25
-
25
ns
t
DW
Data to Write Time Overlap
25
-
30
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
5
-
5
-
ns
Notes: t
CHZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A62L256R-70LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-55LL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-55LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-70LL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
| A62L256V-70LLU | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT LOW VOLTAGE CMOS SRAM |
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