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參數(shù)資料
| 型號(hào)： | A61L73081 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128K X 8 BIT HIGH SPEED CMOS SRAM |
| 中文描述： | 128K的× 8位高速CMOS SRAM的 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | A61L73081 |
A61L73081 Series
(April, 2001, Version 1.0)
7
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 1
(6)
(Write Enable Controlled)
t
WC
Address
D
IN
t
OW7
t
DH
t
DW
t
WHZ7
t
WP2
t
AS1
(4)
t
CW5
t
AW
t
WR3
D
OUT
WE
CE
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
D
IN
t
DW
t
WHZ
t
AW
t
WR3
D
OUT
t
DH
(4)
t
WP2
t
CW5
t
AS1
CE
WE
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low
CE
and a low
WE
.
3. t
WR
is measured from the earliest of
CE
or
WE
going high to the end of the Write cycle
4. If the
CE
low transition occurs simultaneously with the
WE
low transition or after the
WE
transition, outputs
remain in a high impedance state.
5. t
CW
is measured from the later of
CE
going low to the end of Write.
6.
OE
is continuously low. (
OE
= V
IL
)
7. Transition is measured
±
200mV from steady state. This parameter is sampled and not 100% tested.
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