
11
A6150
Timer Clearing and RES Action
The watchdog circuit monitore the activity of the proces-
sor. If the user’s software does not send a pulse to the
TCL input within the programmed open window timeout
period a short watchdog RES pulse is generated which
is equal to T
/40 = 2.5 ms typically (see Fig. 5).
With the open window constraint new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution) it will cause the system to be reset.
If software is stuck in a loop which includes the routine
to clear the watchdog then a conventional watchdog
would not make a system reset even though software is
malfunctioning; the A6150 would make a system reset
because the watchdog would be cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves
of period (T
+ T
+ T
). The watchdog will remain
in this state until the next TCL falling edge appears
during an open window, or until a fresh power-up se-
quence. The system enable output, EN , can be used to
prevent critical control functions being activated in the
event of the system going into this failure mode (see
section “Enable-EN Output”).
The RES output must be pulled up to V
even if the
output is not used by the system (see Fig 18).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrat-
ed by the sequence of events shown in Fig. 6. On pow-
er-up, when the voltage at V
reaches V
, the power-
on-reset, POR, delay is initialized and holds RES active
for the time of the POR delay. A TCL pulse will have no
effect until this power-on-reset delay is completed. When
the risk exists that TCL temporarily floats, e.g. during
T
, a pull-up to V
is required on that pin. After the
POR delay has elapsed, RES goes inactive and the
watchdog timer starts acting. If no TCL pulse occurs,
RES goes active low for a short time T
after each
closed and open window period. A TCL pulse coming
during the open window clears the watchdog timer.
When the TCL pulse occurs too early (during the closed
window), RES goes active and a new timeout sequence
starts. A voltage drop below the V
level for longer than
typically 5
μ
s overrides the timer and immediately forces
RES active and EN inactive. Any further TCL pulse
has no effect until the next power-up sequence has
completed.
Enable - EN Output
The system enable output, EN ,is inactive always when
RES is active and remains inactive after a RES pulse
until the watchdog is serviced correctly 3 consecutive
times (ie. the TCL pulse must come in the open win-
dow). After three consecutive services of the watchdog
with TCL during the open window, the EN goes active
low.
A malfunctioning system would be repeatedly reset by
the watchdog. In a conventional system critical motor
controls could be energized each time reset goes inac-
tive (time allowed for the system to restart) and in this
way the electrical motors driven by the system could
function out of control. The A6150 prevents the above
failure mode by using the EN output to disable the motor
controls until software has successfully cleared the
watchdog three times (ie. the system has correctly re-
started after a reset condition).
For the version A0 the EN output must be pulled up to
V
even if the output is not used by the system (see
Fig. 18.
Typical Application
INPUT OUTPUT
A6150
R
V
SS
22
μ
F
+
+
Regulated voltage
Fig.18
Unregulated voltage
GND
100 k
100 nF
10
μ
F
R1
R2
Address
decoder
Microprocessor
RES
Motor
controls
EN
V
IN
TCL
RES
EN
Version A0:
Version A1: