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參數(shù)資料
| 型號(hào)： | A6130 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | High Efficiency Linear Power Supply with Accurate Power Surveillance and Software Monitoring |
| 中文描述： | 高效率線性電源，電源監(jiān)控和準(zhǔn)確監(jiān)測(cè)軟件 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 500K |
| 代理商： | A6130 |
Pin Description
Pin
Name
Function
1
2
EN
RES
Push-pull active low enable output
Open drain active low reset output.
RES must be pulled up to V
OUTPUT
even if unused
Watchdog timer clear input signal
GND terminal
Voltage regulator input
Voltage regulator output
R
EXT
input for RC oscillator tuning
Voltage comparator input
3
4
5
6
7
8
TCL
V
SS
INPUT
OUTPUT
R
V
IN
Table 5
Functional Description
Voltage Regulator
The A6130 has a 5 V ± 2%, 100 mA, low dropout voltage
regulator. The low supply current (typ. 155 μA) makes the
A6130 particularly suited to automotive systems then re-
mainenergized24hoursaday.Theinputvoltagerangeis
2.3 V to 26 V for operation and the input protection in-
cludesbothreversebattery(20Vbelowground)andload
dump (positive transients up to 60 V). There is no reverse
current flow from the OUTPUT to the INPUT when the
INPUT equals V
SS
. This feature is important for systems
which need to implement (with capacitance) a minimum
power supply hold-up time in the event of power failure.
To achieve good load regulation a 22 μF capacitor (or
greater) is needed on the INPUT (see Fig. 8). Tantalum or
aluminium electrolytics are adequate for the 22 μF capac-
itor; film types will work but are relatively expensive. Many
aluminium electrolytics have electrolytes that freeze at
about -30°C, so tantalums are recommended for opera-
tion below -25°C. The important parameters of the 22 μF
capacitor are an effective series re sistance of
a resonant frequency above 500 kHz.
A 10 μF capacitor (or greater) and a 100 nF capacitor are
required on the OUTPUT to prevent oscillations due to in-
stability. The specification of the 10 μF capacitor is as per
the 22 μF capacitor on the INPUT (see previous para-
graph).
The A6130 will remain stable and in regulation with no ex-
ternal load and the dropout voltage is typically constant
as the input voltage fall to below its minimum level (see
Table 2). These features are especially important in
CMOS RAM keep-alive applications.
Care must be taken not to exceed the maximum junction
temperature (+85°C). The power dissipation within the
A6130 is given by the formula:
P
TOTAL
= (V
INPUT
- V
OUTPUT
) . I
OUTPUT
+ (V
INPUT
) . I
SS
The maximum continuous power dissipation at a given
temperature can be calculated using the formula:
P
MAX
= (85°C - T
A
) / R
th(j-a)
where R
th(j-a)
is the thermal resistance from the junction to
the ambient and is specified in Table 2. Note the R
th(j-a)
given in Table 2 assumes that the package is soldered to
a PCB. The above formula for maximum power dissipa-
5
and
tion assumes a constant load (ie.
thermal resistance for a single pulse is much lower than
the continuous value. For example the A6130 in DIP8
package will have an effective thermal resistance from
the junction to the ambient of about 10°C/W for a single
100 ms pulse.
100 s). The transient
V
IN
Monitoring
The power-on reset and the power-down reset are gener-
ated as a response to the external voltage level applied
on the V
IN
input. The V
DD
voltage at which reset is asserted
or released is determined by the external voltage divider
between V
DD
and V
SS
, as shown on Fig. 8. A part of V
DD
is
compared to the internal voltage reference. To determine
the values of the divider, the leakage current at V
IN
must
be taken into account, as well as the current consump-
tionofthedivideritself.Lowresistorvalueswillneedmore
current, but high resistor values will make the reset
threshold less accurate at high temperature, due to a
possible leakage current at the V
IN
input. The sum of the
two resistors should stay below 300 k
. The formula is:
V
RESET
= V
REF
*(1 + R
1
/R
2
).
Example: choosing R
1
= 100 k
and R
2
= 36 k
will re-
sult in a V
DD
reset threshold of 4.42 V (typ.).
At power-up the reset output (RES) is held low (see Fig.
4). After INPUT reaches 3.36 V (and so OUTPUT reaches
at least 3 V) and V
IN
becomes greater than V
REF
, the RES
output is held low for an additional power-on-reset (POR)
delay which is equal to the watchdog time T
WD
(typically
100 ms with an external resistor of 118 k
pin). The POR delay prevents repeated toggling of RES
even if V
IN
and the INPUT voltage drops out and recovers.
The POR delay allows the microprocessor’s crystal oscil-
lator time to start and stabilize and ensures correct recog-
nition of the reset signal to the microprocessor.
The RES output goes active low generating the
power-down reset whenever V
IN
falls below V
REF
. The sen-
sitivity or reaction time of the internal comparator to the
voltage level on V
IN
is typically 5 μs.
connected at R
Timer Programming
The on-chip oscillator with an external resistor R
EXT
con-
nected between the R pin and V
SS
(see Fig. 8) allows the
user to adjust the power-on reset (POR) delay, watchdog
time T
WD
and with this also the closed and open time win-
dowsaswellasthewatchdogresetpulsewidth(T
WD
/40).
With R
EXT
= 118 k
typical values are:
- Power-on reset delay:
T
POR
is 100 ms
- Watchdog time:
T
WD
is 100 ms
- Closed window:
T
CW
is 80 ms
- Open window:
T
OW
is 40 ms
- Watchdog reset:
T
WDR
is 2.5 ms
Note: the current consumption increases as the fre-
quency increases.
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a
“closed" window and an “open" window (see Fig. 3) and
is defined by two parameters, T
WD
and the Open Window
Percentage (OWP). The closed window starts just after
6
A6130
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