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參數(shù)資料
| 型號(hào)： | A5821 |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | BiMOS II 8-Bit Serial Input Latched Drivers |
| 中文描述： | BiMOS II 8位串行輸入鎖存驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 246K |
| 代理商： | A5821 |
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TIMING CONDITIONS
(V
DD
= 5.0 V, T
A
= +25
°
C, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................
75 ns
Minimum Data Active Time After Clock Pulse
(Data Hold Time) ...........................................................................
75 ns
Minimum Data Pulse Width ..............................................................
150 ns
Minimum Clock Pulse Width ............................................................
150 ns
Minimum Time Between Clock Activation and Strobe.......................
30 ns
Minimum Strobe Pulse Width...........................................................
100 ns
Typical Time Between Strobe Activation and
Output Transition ..........................................................................
1.0
μ
s
B.
C.
D.
E.
F.
G.
TRUTH TABLE
Serial
Data
Input
Shift Register Contents
Serial
Data
Output
Latch Contents
Output Contents
Output
.............. I
8
Enable
Clock
Input I
1
Strobe
Input
I
2
I
3
.............. I
8
I
1
I
2
I
3
I
1
I
2
I
3
.............. I
8
H
H
R
1
R
2
.............. R
7
R
1
R
2
.............. R
7
R
1
R
2
R
3
.............. R
8
X
X
X
R
7
R
7
R
8
X
L
L
X
.............. X
L
R
1
R
2
R
3
.............. R
8
P
1
P
2
P
3
.............. P
8
X
X
X
P
1
P
2
P
3
.............. P
8
P
8
H
L
P
1
P
2
P
3
.............. P
8
H
H
H
.............. H
.............. X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Dwg. No. A-12,627
Serial Data present at the input is
transferred to the shift register on the
logic “0” to logic “1” transition of the
CLOCK input pulse. On succeeding
CLOCK pulses, the registers shift data
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
version). The latches will continue to
accept new data as long as the STROBE
is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
high during serial data entry.
When the ENABLE input is high, all
of the output buffers are disabled (OFF)
without affecting the information stored
in the latches or shift register. With the
ENABLE input low, the outputs are
controlled by the state of the latches.
A
D
B
C
E
F
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
OUT
N
G
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