Table 2-40 A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V
參數(shù)資料
型號: A54SX72A-1CQ208B
廠商: Microsemi SoC
文件頁數(shù): 78/108頁
文件大?。?/td> 0K
描述: IC FPGA SX-A 108K 208-CQFP
標準包裝: 1
系列: SX-A
LAB/CLB數(shù): 6036
輸入/輸出數(shù): 171
門數(shù): 108000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 208-BFCQFP,帶拉桿
供應商設備封裝: 208-CQFP(75x75)
SX-A Family FPGAs
v5.3
2-51
Table 2-40 A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
Parameter
Description
–3 Speed1
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
3.3 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
2.3
2.7
3.0
3.6
5.0
ns
tDHL
Data-to-Pad High to Low
2.5
2.9
3.2
3.8
5.3
ns
tENZL
Enable-to-Pad, Z to L
1.4
1.7
1.9
2.2
3.1
ns
tENZH
Enable-to-Pad, Z to H
2.3
2.7
3.0
3.6
5.0
ns
tENLZ
Enable-to-Pad, L to Z
2.5
2.8
3.2
3.8
5.3
ns
tENHZ
Enable-to-Pad, H to Z
2.5
2.9
3.2
3.8
5.3
ns
dTLH
3
Delta Low to High
0.025
0.03
0.04
0.045
ns/pF
dTHL
3
Delta High to Low
0.015
0.025
ns/pF
3.3 V LVTTL Output Module Timing4
tDLH
Data-to-Pad Low to High
3.2
3.7
4.2
5.0
6.9
ns
tDHL
Data-to-Pad High to Low
3.2
3.7
4.2
4.9
6.9
ns
tDHLS
Data-to-Pad High to Low—low slew
10.3
11.9
13.5
15.8
22.2
ns
tENZL
Enable-to-Pad, Z to L
2.2
2.6
2.9
3.4
4.8
ns
tENZLS
Enable-to-Pad, Z to L—low slew
15.8
18.9
21.3
25.4
34.9
ns
tENZH
Enable-to-Pad, Z to H
3.2
3.7
4.2
5.0
6.9
ns
tENLZ
Enable-to-Pad, L to Z
2.9
3.3
3.7
4.4
6.2
ns
tENHZ
Enable-to-Pad, H to Z
3.2
3.7
4.2
4.9
6.9
ns
dTLH
3
Delta Low to High
0.025
0.03
0.04
0.045
ns/pF
dTHL
3
Delta High to Low
0.015
0.025
ns/pF
dTHLS
3
Delta High to Low—low slew
0.053
0.067
0.073
0.107
ns/pF
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 10 pF loading and 25
Ω resistance.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
相關PDF資料
PDF描述
HMM44DSAN CONN EDGECARD 88POS R/A .156 SLD
EP4SGX290FH29I4 IC STRATIX IV FPGA 290K 780HBGA
HSM44DSAH CONN EDGECARD 88POS R/A .156 SLD
HMM44DSAH CONN EDGECARD 88POS R/A .156 SLD
EP4SGX290FH29C3 IC STRATIX IV FPGA 290K 780HBGA
相關代理商/技術參數(shù)
參數(shù)描述
A54SX72A-1CQ208M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 250MHZ 0.25UM/0.22UM 2.5V 208 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 108K GATES 208CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 171 I/O 208CQFP
A54SX72A-1CQ256 功能描述:IC FPGA SX-A 108K 256-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:SX-A 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應商設備封裝:352-CQFP(75x75)
A54SX72A-1CQ256B 功能描述:IC FPGA SX-A 108K 256-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:SX-A 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA(27x27)
A54SX72A-1CQ256M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 250MHZ 0.25UM/0.22UM 2.5V 256 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 213 I/O 256CQFP
A54SX72A-1CQ256MX3 制造商:Microsemi Corporation 功能描述:SX-A 72K GATE 4024 MC 250MHZ MILITARY ANTIFUSE 2.5/3.3/5V 25 - Trays