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  • 參數(shù)資料
    型號: A54SX32P-1VQ208I
    廠商: Electronic Theatre Controls, Inc.
    元件分類: FPGA
    英文描述: 54SX Family FPGAs
    中文描述: 54SX家庭的FPGA
    文件頁數(shù): 18/57頁
    文件大?。?/td> 415K
    代理商: A54SX32P-1VQ208I
    5 4 S X F a m ily F P G A s
    18
    v3.1
    E v a lua t ing P ow e r in 5 4 S X De v ic e s
    A critical element of system reliability is the ability of
    electronic devices to safely dissipate the heat generated
    during operation. The thermal characteristics of a circuit
    depend on the device and package used, the operating
    temperature, the operating current, and the systems ability
    to dissipate heat.
    You should complete a power evaluation early in the design
    process to help identify potential heat-related problems in
    the system and to prevent the system from exceeding the
    device’s maximum allowed junction temperature.
    The actual power dissipated by most applications is
    significantly lower than the power the package can
    dissipate. However, a thermal analysis should be performed
    for all projects. To perform a power evaluation, follow these
    steps:
    Estimate the power consumption of the application.
    Calculate the maximumpower allowed for the device and
    package.
    Compare the estimated power and maximumpower
    values.
    E s t im a t ing P ow e r C ons um pt ion
    The total power dissipation for the 54SX family is the sum of
    the DC power dissipation and the AC power dissipation. Use
    Equation1 to calculate the estimated power consumption of
    your application.
    P
    Total
    = P
    DC
    + P
    AC
    (1)
    DC P ow e r Dis s ipa t ion
    The power due to standby current is typically a small
    component of the overall power. The Standby power is
    shown below for commercial, worst case conditions (70
    °
    C).
    The DC power dissipation is defined in Equation 2 as
    follows:
    P
    DC
    = (I
    standby
    )*V
    CCA
    + (I
    standby
    )*V
    CCR
    +
    (I
    standby
    )*V
    CCI
    + x*V
    OL
    *I
    OL
    + y*(V
    CCI
    – V
    OH
    )*V
    OH
    (2)
    A C P ow e r Dis s ipa t ion
    The power dissipation of the 54SX Family is usually
    dominated by the dynamic power dissipation. Dynamic
    power dissipation is a function of frequency, equivalent
    capacitance and power supply voltage. The AC power
    dissipation is defined as follows:
    P
    AC
    = P
    Module
    + P
    RCLKA Net
    + P
    RCLKB Net
    + P
    HCLK Net
    +
    P
    Output Buffer
    + P
    Input Buffer
    P
    AC
    = V
    CCA2
    * [(m * C
    EQM
    * f
    m
    )
    Module
    +
    (n * C
    EQI
    * f
    n
    )
    Input Buffer
    + (p * (C
    EQO
    + C
    L
    ) * f
    p
    )
    Output Buffer
    +
    (0.5 * (q
    1
    * C
    EQCR
    * f
    q1
    ) + (r
    1
    * f
    q1
    ))
    RCLKA
    +
    (0.5 * (q
    2
    * C
    EQCR
    * f
    q2
    )+ (r
    2
    * f
    q2
    ))
    RCLKB
    +
    (0.5 * (s
    1
    * C
    EQHV
    * f
    s1
    ) + (C
    EQHF
    * f
    s1
    ))
    HCLK
    ]
    (3)
    (4)
    De finit ion of T e rm s U s e d in F orm ula
    m
    = Number of logic modules switching at f
    m
    n
    = Number of input buffers switching at f
    n
    p
    = Number of output buffers switching at f
    p
    q
    1
    = Number of clock loads on the first routed array
    clock
    q
    2
    = Number of clock loads on the second routed
    array clock
    x
    = Number of I/Os at logic low
    y
    = Number of I/Os at logic high
    r
    1
    = Fixed capacitance due to first routed array
    clock
    r
    2
    = Fixed capacitance due to second routed array
    clock
    s
    1
    = Number of clock loads on the dedicated array
    clock
    C
    EQM
    = Equivalent capacitance of logic modules in pF
    C
    EQI
    = Equivalent capacitance of input buffers in pF
    C
    EQO
    = Equivalent capacitance of output buffers in pF
    C
    EQCR
    = Equivalent capacitance of routed array clock in
    pF
    C
    EQHV
    = Variable capacitance of dedicated array clock
    C
    EQHF
    = Fixed capacitance of dedicated array clock
    C
    L
    = Output lead capacitance in pF
    f
    m
    = Average logic module switching rate in MHz
    f
    n
    = Average input buffer switching rate in MHz
    f
    p
    = Average output buffer switching rate in MHz
    f
    q1
    = Average first routed array clock rate in MHz
    f
    q2
    = Average second routed array clock rate in MHz
    f
    s1
    = Average dedicated array clock rate in MHz
    A54SX08 A54SX16 A54SX16P A54SX32
    C
    EQM
    (pF) 4.0
    4.0
    C
    EQI
    (pF)
    3.4
    3.4
    C
    EQO
    (pF) 4.7
    4.7
    C
    EQCR
    (pF) 1.6
    1.6
    C
    EQHV
    0.615
    0.615
    C
    EQHF
    60
    96
    r
    1
    (pF)
    87
    138
    r
    2
    (pF)
    87
    138
    Table 3
    I
    CC
    4mA
    V
    CC
    3.6V
    Power
    14.4mW
    4.0
    3.4
    4.7
    1.6
    0.615
    96
    138
    138
    4.0
    3.4
    4.7
    1.6
    0.615
    140
    171
    171
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