Figure 1-13 Output Buffer Delays Figure 1-14 AC Test Loads To AC Test Loads (shown below) PAD D E TRIBUFF I" />
參數(shù)資料
型號: A54SX32-1TQG176
廠商: Microsemi SoC
文件頁數(shù): 19/64頁
文件大?。?/td> 0K
描述: IC FPGA SX 48K GATES 176-TQFP
標準包裝: 40
系列: SX
LAB/CLB數(shù): 2880
輸入/輸出數(shù): 147
門數(shù): 48000
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 176-LQFP
供應(yīng)商設(shè)備封裝: 176-TQFP(24x24)
SX Family FPGAs
1- 22
v3.2
Figure 1-13 Output Buffer Delays
Figure 1-14 AC Test Loads
To AC Test Loads (shown below)
PAD
D
E
TRIBUFF
In
50%
Out
V
OL
1.5 V
50%
1.5 V
En
50%
Out
V
OL
1.5 V
50%
10%
En
50%
Out
GND
1.5 V
50%
90%
t
DLH
t
DHL
t
ENZL
t
ENLZ
t
ENZH
t
ENHZ
V
OH
V
OH
GND
VCC
GND
V
CC
V
CC
V
CC
GND
Load 2
(used to measure
disable delays)
V
CC
GND
35 pF
R to VCC for tPLZ
R to GND for t
PHZ
R = 1 k
Ω
Load 1
(used to measure
propagation delay)
Load 2
(used to measure
enable delays)
35 pF
To Output
Under Test
V
CC
GND
35 pF
R to V
CC for tPLZ
R to GND for t
PHZ
R = 1 k
Ω
To Output
Under Test
To Output
Under Test
Figure 1-15 Input Buffer Delays
PAD
Y
INBUF
In
3 V
0 V
1.5 V
Out
GND
V
CC
50%
t
INY
1.5 V
50%
t
INY
Figure 1-16 C-Cell Delays
S
A
B
Y
S, A ,or B
Out
50%
t
PD
Out
50%
t
PD
tPD
t
PD
V
CC
GND
VCC
GND
V
CC
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