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參數(shù)資料
| 型號： | A54SX32-1TQ176 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 2/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SX 48K GATES 176-TQFP |
| 標準包裝： | 40 |
| 系列： | SX |
| LAB/CLB數(shù)： | 2880 |
| 輸入/輸出數(shù)： | 147 |
| 門數(shù)： | 48000 |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 176-LQFP |
| 供應商設備封裝： | 176-TQFP（24x24） |
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SX Family FPGAs
1- 6
v3.2
Boundary Scan Testing (BST)
All SX devices are IEEE 1149.1 compliant. SX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test
pins in conjunction with the program fuse. The
functionality of each pin is described in Table 1-2. In the
dedicated test mode, TCK, TDI, and TDO are dedicated
pins and cannot be used as regular I/Os. In flexible mode,
TMS should be set HIGH through a pull-up resistor of
10 k
Ω. TMS can be pulled LOW to initiate the test
sequence.
The program fuse determines whether the device is in
dedicated or flexible mode. The default (fuse not blown)
is flexible mode.
Dedicated Test Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, users need to reserve the JTAG
pins in Actel's Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard"
(Figure 1-7). JTAG pins comply with LVTTL/TTL I/O
specification regardless of whether they are used as a
user I/O or a JTAG I/O. Refer to the Table 1-5 on page 1-8
for detailed specifications.
Development Tool Support
The SX family of FPGAs is fully supported by both the
Actel Libero Integrated Design Environment (IDE) and
Designer FPGA Development software. Actel Libero IDE
is
a
design
management
environment,
seamlessly
integrating design tools while guiding the user through
the design flow, managing all design and log files, and
passing necessary design data among tools. Libero IDE
allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design
in a single environment. Libero IDE includes Synplify for
Actel from Synplicity, ViewDraw for Actel from
Mentor Graphics, ModelSim HDL Simulator from
Mentor
Graphics,
WaveFormer
Lite
from
SynaptiCAD, and Designer software from Actel. Refer
to the Libero IDE flow diagram (located on the Actel
website) for more information.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven
place-and-route,
and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results
of place-and-route. Additionally, the back-annotation
flow is compatible with all the major simulators, and the
simulation results can be cross-probed with Silicon
Explorer II, Actel integrated verification and logic
analysis tool. Another tool included in the Designer
software is the SmartGen core generator, which easily
creates popular and commonly used logic functions for
implementation into your schematic or HDL design. Actel
Designer software is compatible with the most popular
FPGA design entry and verification tools from companies
such as Mentor Graphics, Synplicity, Synopsys, and
Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
Probe Circuit Control Pins
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to
the PRA/PRB pins for observation. Figure 1-8 on page 1-7
illustrates the interconnection between Silicon Explorer II
and the FPGA to perform in-circuit verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Because these pins are
active during probing, critical signals input through
these pins are not available while probing. In addition,
the Security Fuse should not be programmed because
doing so disables the Probe Circuitry.
Table 1-2
Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are dedicated
BST pins.
TCK, TDI, TDO are flexible and
may be used as I/Os.
No need for pull-up resistor for
TMS
Use a pull-up resistor of 10 k
Ω
on TMS.
Figure 1-7 Device Selection Wizard
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| A54SX32-1TQ176I | 功能描述:IC FPGA SX 48K GATES 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| A54SX32-1TQG144 | 功能描述:IC FPGA SX 48K GATES 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| A54SX32-1TQG144I | 功能描述:IC FPGA SX 48K GATES 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
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