參數(shù)資料
型號： A54SX16A-2TQ208M
廠商： Electronic Theatre Controls, Inc.
英文描述： LM20242 36V, 2A PowerWise ® Adjustable Frequency Synchronous Buck Regulator; Package: TSSOP EXP PAD; No of Pins: 20; Qty per Container: 250; Container: Reel
中文描述： 的SX - A系列FPGA的
文件頁數(shù)： 11/108頁
文件大?。?/td> 720K
代理商： A54SX16A-2TQ208M
SX-A Family FPGAs
v5.1
1-5
Clock Resources
Actel’s high-drive routing structure provides three clock
networks (
Table 1-1
). The first clock, called HCLK, is
hardwired from the HCLK buffer to the clock select
multiplexor (MUX) in each R-cell. HCLK cannot be
connected to combinatorial logic. This provides a fast
propagation path for the clock signal. If not used, this
pin must be set as Low or High on the board. It must not
be left floating.
Figure 1-7
describes the clock circuit
used for the constant load HCLK and the macros
supported.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB pins are not used or sourced from signals,
these pins must be set as Low or High on the board. They
must not be left floating.
Figure 1-8
describes the CLKA
and CLKB circuit used and the macros supported in SX-A
devices with the exception of A54SX72A.
In addition, the A54SX72A device provides four
quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD—
corresponding to bottom-left, bottom-right, top-left,
and top-right locations on the die, respectively), which
can be sourced from external pins or from internal logic
signals within the device. Each of these clocks can
individually drive up to an entire quadrant of the chip,
or they can be grouped together to drive multiple
quadrants (
Figure 1-9 on page 1-6
). QCLK pins can
function as user I/O pins. If not used, the QCLK pins
must be tied Low or High on the board and must not be
left floating.
For more information on how to use quadrant clocks in
Global Clock Networks
RT54SX72S Quadrant Clocks
相關(guān)PDF資料
PDF描述
A54SX16A-3BG208 LM20242 36V, 2A PowerWise ® Adjustable Frequency Synchronous Buck Regulator; Package: TSSOP EXP PAD; No of Pins: 20; Qty per Container: 2500; Container: Reel
A54SX16A-3BG208A SX-A Family FPGAs
A54SX16A-FCQ208B LM231A/LM231/LM331A/LM331 Precision Voltage-to-Frequency Converters; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail
A54SX16A-FCQ208I LM231A/LM231/LM331A/LM331 Precision Voltage-to-Frequency Converters; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail
A54SX16A-FCQ208M LM134/LM234/LM334 3-Terminal Adjustable Current Sources; Package: TO-46; No of Pins: 3; Qty per Container: 1000; Container: Box
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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