tINYH Input Data Pad to Y High 5 V PCI 0.5 0.6 0.7 0.9 ns " />
參數(shù)資料
型號: A54SX16A-1TQG100
廠商: Microsemi SoC
文件頁數(shù): 51/108頁
文件大小: 0K
描述: IC FPGA SX 24K GATES 100-TQFP
標準包裝: 90
系列: SX-A
LAB/CLB數(shù): 1452
輸入/輸出數(shù): 81
門數(shù): 24000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
SX-A Family FPGAs
v5.3
2-27
tINYH
Input Data Pad to Y High 5 V PCI
0.5
0.6
0.7
0.9
ns
tINYL
Input Data Pad to Y Low 5 V PCI
0.7
0.8
0.9
1.1
1.5
ns
tINYH
Input Data Pad to Y High 5 V TTL
0.6
0.7
0.9
ns
tINYL
Input Data Pad to Y Low 5 V TTL
0.7
0.8
0.9
1.1
1.5
ns
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
0.3
0.4
0.6
ns
tIRD2
FO = 2 Routing Delay
0.4
0.5
0.6
0.8
ns
tIRD3
FO = 3 Routing Delay
0.5
0.6
0.7
0.8
1.1
ns
tIRD4
FO = 4 Routing Delay
0.7
0.8
0.9
1.0
1.4
ns
tIRD8
FO = 8 Routing Delay
1.2
1.4
1.5
0.8
2.5
ns
tIRD12
FO = 12 Routing Delay
1.7
2.0
2.2
2.6
3.6
ns
Table 2-21 A54SX16A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
Parameter
Description
–3 Speed1
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
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