參數(shù)資料
型號: A54SX16A-1BG208M
廠商: Electronic Theatre Controls, Inc.
元件分類: FPGA
英文描述: SX-A Family FPGAs
中文描述: 的SX - A系列FPGA的
文件頁數(shù): 71/108頁
文件大?。?/td> 720K
代理商: A54SX16A-1BG208M
SX-A Family FPGAs
v5.1
2-51
Table 2-40
A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions V
CCA
= 2.25 V, V
CCI
= 3.0 V, T
J
= 70°C)
Parameter
3.3 V PCI Output Module Timing
1
Description
–3 Speed
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
DLH
Data-to-Pad Low to High
2.3
2.7
3.0
3.6
5.0
ns
t
DHL
Data-to-Pad High to Low
2.5
2.9
3.2
3.8
5.3
ns
t
ENZL
Enable-to-Pad, Z to L
1.4
1.7
1.9
2.2
3.1
ns
t
ENZH
Enable-to-Pad, Z to H
2.3
2.7
3.0
3.6
5.0
ns
t
ENLZ
Enable-to-Pad, L to Z
2.5
2.8
3.2
3.8
5.3
ns
t
ENHZ
d
TLH2
d
THL2
3.3 V LVTTL Output Module Timing
3
Enable-to-Pad, H to Z
2.5
2.9
3.2
3.8
5.3
ns
Delta Low to High
0.025
0.03
0.03
0.04
0.045
ns/pF
Delta High to Low
0.015
0.015
0.015
0.015
0.025
ns/pF
t
DLH
Data-to-Pad Low to High
3.2
3.7
4.2
5.0
6.9
ns
t
DHL
Data-to-Pad High to Low
3.2
3.7
4.2
4.9
6.9
ns
t
DHLS
Data-to-Pad High to Low—low slew
10.3
11.9
13.5
15.8
22.2
ns
t
ENZL
Enable-to-Pad, Z to L
2.2
2.6
2.9
3.4
4.8
ns
t
ENZLS
Enable-to-Pad, Z to L—low slew
15.8
18.9
21.3
25.4
34.9
ns
t
ENZH
Enable-to-Pad, Z to H
3.2
3.7
4.2
5.0
6.9
ns
t
ENLZ
Enable-to-Pad, L to Z
2.9
3.3
3.7
4.4
6.2
ns
t
ENHZ
d
TLH2
d
THL2
d
THLS2
Enable-to-Pad, H to Z
3.2
3.7
4.2
4.9
6.9
ns
Delta Low to High
0.025
0.03
0.03
0.04
0.045
ns/pF
Delta High to Low
0.015
0.015
0.015
0.015
0.025
ns/pF
Delta High to Low—low slew
0.053
0.053
0.067
0.073
0.107
ns/pF
Notes:
1. Delays based on 10 pF loading and 25
resistance.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V
CCI
value into the following equation:
Slew Rate [V/ns] = (0.1*V
CCI
– 0.9*V
CCI)
/ (C
load
* d
T[LH|HL|HLS]
)
where C
load
is the load capacitance driven by the I/O in pF
d
T[LH|HL|HLS]
is the worst case delta value from the datasheet in ns/pF.
3. Delays based on 35 pF loading.
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