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參數(shù)資料
| 型號： | A54SX16-FG208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LM20123 3A, 1.5MHz PowerWise ® Synchronous Buck Regulator; Package: TSSOP EXP PAD; No of Pins: 16; Qty per Container: 2500; Container: Reel |
| 中文描述： | 54SX家庭的FPGA |
| 文件頁數(shù)： | 15/57頁 |
| 文件大?。?/td> | 415K |
| 代理商： | A54SX16-FG208 |
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v3.1
15
5 4 S X F a m ily F P G A s
A 54S X 16P AC S pec ific ations (3.3V PCI Operation)
Symbol
Parameter
Condition
0 < V
OUT
≤
0.3V
CC1
0.3V
CC
≤
V
OUT
< 0.9V
CC1
Min.
Max.
Units
Switching Current High
mA
mA
–12V
CC
I
OH(AC)
0.7V
CC
< V
OUT
< V
CC1, 2
–17.1 + (V
CC
– V
OUT
)
Equation C: on
page 16
–32V
CC
(Test Point)
V
OUT
= 0.7V
CC2
V
CC
> V
OUT
≥
0.6V
CC1
0.6V
CC
> V
OUT
> 0.1V
CC1
0.18V
CC
> V
OUT
> 0
1, 2
V
OUT
= 0.18V
CC2
–3 < V
IN
≤
–1
–3 < V
IN
≤
–1
0.2V
CC
to 0.6V
CC
load
0.6V
CC
to 0.2V
CC
load
mA
mA
mA
mA
Switching Current High
16V
CC
26.7V
OUT
I
OL(AC)
on page 16
38V
CC
(Test Point)
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
3
Output Fall Slew Rate
3
I
CL
I
CH
slew
R
slew
F
Notes:
1.
–25 + (V
IN
+ 1)/0.015
25 + (V
IN
– V
OUT
– 1)/0.015
1
1
mA
mA
V/ns
V/ns
4
4
Refer to the V/I curves in
Figure9
. Switching current characteristics for REQ#and GNT#are permitted to be one half of that specified here;
i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#which are system outputs.
“Switching Current High” specification are not relevant to SERR# INTA# INTB# INTC# and INTD#which are open drain outputs.
Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)
are provided with the respective diagrams in
Figure9
. The equation defined maxima should be met by design. In order to facilitate
component testing, a maximum current test point is defined for each side of the output driver.
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
2.
3.
output
buffer
1/2 in. max.
V
CC
1k
10 pF
1k
pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX16-FG208I | 54SX Family FPGAs |
| A54SX16-FG208M | LM20124 4A, 1MHz PowerWise ® Synchronous Buck Regulator; Package: TSSOP EXP PAD; No of Pins: 16; Qty per Container: 92; Container: Rail |
| A54SX16-FG208PP | LM20124 4A, 1MHz PowerWise ® Synchronous Buck Regulator; Package: TSSOP EXP PAD; No of Pins: 16; Qty per Container: 250; Container: Reel |
| A54SX16-PL208 | LM20124 4A, 1MHz PowerWise ® Synchronous Buck Regulator; Package: TSSOP EXP PAD; No of Pins: 16; Qty per Container: 2500; Container: Reel |
| A54SX16-PL208I | 54SX Family FPGAs |
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