參數(shù)資料
型號(hào): A54SX16-2PQ208
廠商: Electronic Theatre Controls, Inc.
元件分類: FPGA
英文描述: 54SX Family FPGAs
中文描述: 54SX家庭的FPGA
文件頁(yè)數(shù): 20/57頁(yè)
文件大?。?/td> 415K
代理商: A54SX16-2PQ208
5 4 S X F a m ily F P G A s
20
v3.1
Step #2:
V
CCA
*V
CCA
m*f
m
*C
EQM
n*f
n
*C
EQI
p*f
p
*(C
EQO
+C
L
)
0.5*(q
1
*C
EQCR
*f
q1
)+(r
1
*f
q1
)
0.5*(q
2
*C
EQCR
*f
q2
)+(r
2
*f
q2
)
0.5 *(s
1
* C
EQHV
* f
s1
)+(C
EQHF
*f
s1
)
P
AC
= 1.461W
Calculate Dynamc Power Consumption
Step #3:
DC Power Dissipation
P
DC
= (I
standby
)*V
CCA
+ (I
standby
)*V
CCR
+ (I
standby
)*V
CCI
+
X*V
OL
*I
OL
+ Y*(V
CCI
– V
OH
)*V
OH
For a rough estimate of DC Power Dissipation, only use
P
DC
= (I
standby
)*V
CCA
. The rest of the formula provides a
very small number that can be considered negligible.
Calculate DC Power Dissipation
(8)
P
DC
= (I
standby
)*V
CCA
P
DC
= .55mA*3.3V
P
DC
= 0.001815W
Step #4:
Calculate Total Power Consumption
P
Total
= P
AC
+ P
DC
P
Total
= 1.461 + 0.001815
P
Total
= 1.4628W
Step #5:
Compare Estimated Power Consumption against
Characterized Power Consumption
The estimated total power consumption for this design is
1.46W. The characterized power consumption for this design
at 200 MHz is 1.0164W.
Figure10
shows the characterized
power dissipation numbers for the shift register design
using frequencies ranging from 1 MHz to 200 MHz.
10.89
0.02112
0.000136
0.000794
0.11208
0
0
Figure 10
Power Dissipation
0
200
400
600
800
1000
1200
Frequency MHz
P
20
0
40
60
80
100
120
140
160
180
200
相關(guān)PDF資料
PDF描述
A54SX16-2PQ208I 54SX Family FPGAs
A54SX16-2PQ208M 54SX family FPGAs
A54SX16-2PQ208PP 54SX family FPGAs
A54SX16-2TQ208 LM193/LM293/LM393/LM2903 Low Power Low Offset Voltage Dual Comparators; Package: CERDIP; No of Pins: 8; Qty per Container: 40; Container: Rail
A54SX16-2TQ208I 54SX Family FPGAs
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