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參數(shù)資料
| 型號： | A54SX08P-FG208PP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LM1876 Overture Audio Power Amplifier Series Dual 20W Audio Power Amplifier with Mute and Standby Modes; Package: TO-220; No of Pins: 15; Qty per Container: 20; Container: Rail |
| 中文描述： | 54SX家庭的FPGA |
| 文件頁數(shù)： | 11/57頁 |
| 文件大?。?/td> | 415K |
| 代理商： | A54SX08P-FG208PP |
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v3.1
11
5 4 S X F a m ily F P G A s
P C I C om plia nc e for t he 5 4 S X F a m ily
The 54SX family supports 3.3V and 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
A 54S X 16P DC S pe c ific a tions (5.0V P C I Ope ra tion)
Symbol
Parameter
Condition
Min.
Max.
Units
V
CCA
V
CCR
V
CCI
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
C
IN
C
CLK
C
IDSEL
Notes:
1.
2.
Supply Voltage for Array
3.0
3.6
V
Supply Voltage required for Internal Biasing
Supply Voltage for IOs
Input High Voltage
1
Input Low Voltage
1
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage
2
Input Pin Capacitance
3
CLK Pin Capacitance
IDSEL Pin Capacitance
4
4.75
4.75
2.0
–0.5
5.25
5.25
V
V
V
V
μA
μA
V
V
pF
pF
pF
V
CC
+ 0.5
0.8
70
–70
V
IN
= 2.7
V
IN
= 0.5
I
OUT
= –2 mA
I
OUT
= 3 mA, 6 mA
2.4
0.55
10
12
8
5
Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include,
FRAME# IRDY# TRDY# DEVSEL# STOP# SERR# PERR# LOCK# and, when used AD[63::32], C/BE[7::4]# PAR64, REQ64# and ACK64#
Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
3.
4.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX08P-PL208 | LM1876 Overture Audio Power Amplifier Series Dual 20W Audio Power Amplifier with Mute and Standby Modes; Package: ISOLATED TO220; No of Pins: 15; Qty per Container: 20; Container: Rail |
| A54SX16-PQ208I | 54SX Family FPGAs |
| A54SX16-PQ208M | LM20133 3A, PowerWise ® Synchronous Buck Regulator with Input Synchronization; Package: TSSOP EXP PAD; No of Pins: 16; Qty per Container: 92; Container: Rail |
| A54SX16-PQ208PP | LM20133 3A, PowerWise ® Synchronous Buck Regulator with Input Synchronization; Package: TSSOP EXP PAD; No of Pins: 16; Qty per Container: 250; Container: Reel |
| A54SX16-TQ208 | LM20133 3A, PowerWise ® Synchronous Buck Regulator with Input Synchronization; Package: TSSOP EXP PAD; No of Pins: 16; Qty per Container: 2500; Container: Reel |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08-PL208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-PL208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-PL208M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-PL208PP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-PL84 | 功能描述:IC FPGA SX 12K GATES 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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