參數資料
型號: A54SX08P-3TQ208PP
廠商: Electronic Theatre Controls, Inc.
元件分類: FPGA
英文描述: 54SX Family FPGAs
中文描述: 54SX家庭的FPGA
文件頁數: 24/57頁
文件大?。?/td> 415K
代理商: A54SX08P-3TQ208PP
5 4 S X F a m ily F P G A s
24
v3.1
T im ing C ha ra c t e ris t ic s
Timing characteristics for 54SX devices fall into three
categories:
family-dependent, device-dependent,
design-dependent.
The
input
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design is complete.
Delay values may then be determined by using the
DirectTime Analyzer utility or performing simulation with
post-layout delays.
and
and
output
buffer
C rit ic a l N e t s a nd T y pic a l N e t s
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
time-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up to
6%of the nets in a design may be designated as critical,
while 90%of the nets in a design are typical.
L ong T ra c k s
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6%of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
T im ing De ra t ing
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
T e m pe ra t ure a nd V olt a g e De ra t ing F a c t ors
(Norma lize d to Wors t-C a s e C omme rc ia l, T
J
= 70
°
C , V
C C A
= 3.0V )
R e g is t e r C e ll T im ing C ha ra c t e ris t ic s
F lip-F lops
(Positive edge triggered)
D
CLK
CLR
Q
D
CLK
Q
CLR
t
HPWH
,
t
RPWH
t
WASYN
t
HD
t
SUD
t
HP
t
HPWL
,
t
RPWL
t
RCO
t
CLR
t
PRESET
PRESET
V
CCA
3.0
3.3
3.6
Junction Temperature (T
J
)
25
–55
–40
0
70
85
125
0.75
0.70
0.66
0.78
0.73
0.69
0.87
0.82
0.77
0.89
0.83
0.78
1.00
0.93
0.87
1.04
0.97
0.92
1.16
1.08
1.02
相關PDF資料
PDF描述
A54SX08P-3VQ208 54SX Family FPGAs
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A54SX32 Quad 2-input positive-NAND gates 8-SO 0 to 70
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相關代理商/技術參數
參數描述
A54SX08P-3TQG208 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
A54SX08-P-3TQG208I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
A54SX08P-3TQG208I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
A54SX08-P-3TQG208M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
A54SX08P-3TQG208M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs