
5 4 S X F a m ily F P G A s
22
v3.1
5 4 S X T im ing Mode l*
H a rd-W ire d C loc k
External Set-Up
= t
INY
+ t
IRD1
+ t
SUD
– t
HCKH
= 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns
Clock-to-Out (Pin-to-Pin)
= t
HCKH
+ t
RCO
+ t
RD1
+ t
DHL
= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns
R out e d C loc k
External Set-Up = t
INY
+ t
IRD1
+ t
SUD
– t
RCKH
= 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns
Clock-to-Out (Pin-to-Pin)
= t
RCKH
+ t
RCO
+ t
RD1
+ t
DHL
= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns
*Values shown for A54SX08-3, worst-case commercial conditions.
Output Delays
Internal Delays
Input Delays
Hard-Wired
Clock
I/O Module
F
HMAX
= 320 MHz
t
INY
= 1.5 ns
t
IRD2
= 0.6 ns
Combinatorial
Cell
t
PD
=0.6 ns
Register
Cell
I/O Module
t
RD1
= 0.3 ns
t
RD4
= 1.0 ns
t
RD8
= 1.9 ns
t
DHL
= 1.6 ns
I/O Module
Routed
Clock
F
MAX
= 250 MHz
D
Q
D
Q
t
DHL
= 1.6 ns
t
ENZH
= 2.3 ns
t
RD1
= 0.3 ns
t
RCO
= 0.8 ns
t
SUD
= 0.5 ns
t
HD
= 0.0 ns
Predicted
Routing
Delays
t
RCKH
= 1.5 ns (100% Load)
t
RD1
= 0.3 ns
Register
Cell
t
RCO
= 0.8 ns
t
HCKH
= 1.0 ns