<wbr id="v7ii9"><form id="v7ii9"></form></wbr>
<ins id="v7ii9"><label id="v7ii9"><dl id="v7ii9"></dl></label></ins>
  • <pre id="v7ii9"></pre>
    參數(shù)資料
    型號(hào): A54SX08A-CQ208I
    廠商: Electronic Theatre Controls, Inc.
    元件分類: FPGA
    英文描述: SX-A Family FPGAs
    中文描述: 的SX - A系列FPGA的
    文件頁(yè)數(shù): 66/108頁(yè)
    文件大?。?/td> 720K
    代理商: A54SX08A-CQ208I
    SX-A Family FPGAs
    2-46
    v5.1
    Table 2-37
    A54SX72A Timing Characteristics
    (Worst-Case Commercial Conditions V
    CCA
    = 2.25 V, V
    CCI
    = 3.0 V, T
    J
    = 70°C)
    Parameter
    Description
    –3 Speed
    –2 Speed
    –1 Speed
    Std. Speed
    –F Speed
    Units
    Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
    Dedicated (Hardwired) Array Clock Networks
    t
    HCKH
    Input Low to High
    (Pad to R-cell Input)
    1.6
    1.9
    2.1
    2.5
    3.8
    ns
    t
    HCKL
    Input High to Low
    (Pad to R-cell Input)
    1.7
    1.9
    2.1
    2.5
    3.8
    ns
    t
    HPWH
    Minimum Pulse Width High
    1.5
    1.7
    2.0
    2.3
    3.2
    ns
    t
    HPWL
    Minimum Pulse Width Low
    1.5
    1.7
    2.0
    2.3
    3.2
    ns
    t
    HCKSW
    Maximum Skew
    1.4
    1.6
    1.8
    2.1
    3.3
    ns
    t
    HP
    Minimum Period
    3.0
    3.4
    4.0
    4.6
    6.4
    ns
    f
    HMAX
    Routed Array Clock Networks
    Maximum Frequency
    333
    294
    250
    217
    156
    MHz
    t
    RCKH
    Input Low to High (Light Load)
    (Pad to R-cell Input)
    2.2
    2.6
    2.9
    3.4
    4.8
    ns
    t
    RCKL
    Input High to Low (Light Load)
    (Pad to R-cell Input)
    2.8
    3.3
    3.7
    4.3
    6.0
    ns
    t
    RCKH
    Input Low to High (50% Load)
    (Pad to R-cell Input)
    2.4
    2.8
    3.2
    3.7
    5.2
    ns
    t
    RCKL
    Input High to Low (50% Load)
    (Pad to R-cell Input)
    2.9
    3.4
    3.8
    4.5
    6.2
    ns
    t
    RCKH
    Input Low to High (100% Load)
    (Pad to R-cell Input)
    2.6
    3.0
    3.4
    4.0
    5.6
    ns
    t
    RCKL
    Input High to Low (100% Load)
    (Pad to R-cell Input)
    3.1
    3.6
    4.1
    4.8
    6.7
    ns
    t
    RPWH
    Minimum Pulse Width High
    1.5
    1.7
    2.0
    2.3
    3.2
    ns
    t
    RPWL
    Minimum Pulse Width Low
    1.5
    1.7
    2.0
    2.3
    3.2
    ns
    t
    RCKSW
    Maximum Skew (Light Load)
    1.9
    2.2
    2.5
    3
    4.1
    ns
    t
    RCKSW
    Maximum Skew (50% Load)
    1.9
    2.1
    2.4
    2.8
    3.9
    ns
    t
    RCKSW
    Quadrant Array Clock Networks
    Maximum Skew (100% Load)
    1.9
    2.1
    2.4
    2.8
    3.9
    ns
    t
    QCKH
    Input Low to High (Light Load)
    (Pad to R-cell Input)
    1.3
    1.5
    1.7
    1.9
    2.7
    ns
    t
    QCHKL
    Input High to Low (Light Load)
    (Pad to R-cell Input)
    1.3
    1.5
    1.7
    2
    2.8
    ns
    t
    QCKH
    Input Low to High (50% Load)
    (Pad to R-cell Input)
    1.5
    1.7
    1.9
    2.2
    3.1
    ns
    t
    QCHKL
    Input High to Low (50% Load)
    (Pad to R-cell Input)
    1.5
    1.8
    2
    2.3
    3.2
    ns
    t
    QCKH
    Input Low to High (100% Load)
    (Pad to R-cell Input)
    1.7
    1.9
    2.2
    2.5
    3.5
    ns
    相關(guān)PDF資料
    PDF描述
    A54SX72A Quad 2-input positive-NOR gates 14-SO 0 to 70
    A54SX72A-1BG208M Quad 2-input positive-NAND gates with open collector outputs 14-SOIC 0 to 70
    A54SX72A-1PQ208 SX-A Family FPGAs
    A54SX72A-1PQ208A SX-A Family FPGAs
    A54SX72A-1PQ208B SX-A Family FPGAs
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    A54SX08A-CQ208M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
    A54SX08A-CQG208 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
    A54SX08A-CQG208A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
    A54SX08A-CQG208B 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
    A54SX08A-CQG208I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs