參數(shù)資料
型號(hào)： A54SX08A-2FGG144I
廠商： Microsemi SoC
文件頁數(shù)： 16/108頁
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 144-FBGA
標(biāo)準(zhǔn)包裝： 160
系列： SX-A
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 111
門數(shù)： 12000
電源電壓： 2.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LBGA
供應(yīng)商設(shè)備封裝： 144-FPBGA（13x13）
SX-A Family FPGAs
v5.3
1-11
Probing Capabilities
SX-A devices also provide an internal probing capability
that is accessed with the JTAG pins. The Silicon Explorer II
diagnostic hardware is used to control the TDI, TCK, TMS,
and TDO pins to select the desired nets for debugging.
The user assigns the selected internal nets in Actel Silicon
Explorer II software to the PRA/PRB output pins for
observation. Silicon Explorer II automatically places the
device into JTAG mode. However, probing functionality is
only activated when the TRST pin is driven high or left
floating, allowing the internal pull-up resistor to pull
TRST High. If the TRST pin is held Low, the TAP controller
remains in the Test-Logic-Reset state so no probing can
be performed. However, the user must drive the TRST pin
High or allow the internal pull-up resistor to pull TRST
High.
When selecting the Reserve Probe Pin box as shown in
Figure 1-12 on page 1-9, direct the layout tool to reserve
the PRA and PRB pins as dedicated outputs for probing.
This Reserve option is merely a guideline. If the designer
assigns user I/Os to the PRA and PRB pins and selects the
Reserve
Probe
Pin option, Designer Layout will
override the Reserve Probe Pin option and place the
user I/Os on those pins.
To allow probing capabilities, the security fuse must not
be programmed. Programming the security fuse disables
the JTAG and probe circuitry. Table 1-9 summarizes the
possible device configurations for probing once the
device leaves the Test-Logic-Reset JTAG state.
Table 1-9 Device Configuration Options for Probe Capability (TRST Pin Reserved)
JTAG Mode
TRST1
Security Fuse Programmed
PRA, PRB2
TDI, TCK, TDO2
Dedicated
Low
No
User I/O3
JTAG Disabled
High
No
Probe Circuit Outputs
JTAG I/O
Flexible
Low
No
User I/O3
High
No
Probe Circuit Outputs
JTAG I/O
Yes
Probe Circuit Secured
Notes:
1. If the TRST pin is not reserved, the device behaves according to TRST = High as described in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
the Designer software.
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參數(shù)描述
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A54SX08A-2PQ208B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
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