
SX-A Family FPGAs
v5.1
2-45
t
QCHKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.9
3.4
3.8
4.5
6.3
ns
t
QPWH
Minimum Pulse Width High
1.5
1.7
2.0
2.3
3.2
ns
t
QPWL
Minimum Pulse Width Low
1.5
1.7
2.0
2.3
3.2
ns
t
QCKSW
Maximum Skew (Light Load)
0.2
0.3
0.3
0.3
0.5
ns
t
QCKSW
Maximum Skew (50% Load)
0.4
0.5
0.5
0.6
0.9
ns
t
QCKSW
Maximum Skew (100% Load)
0.4
0.5
0.5
0.6
0.9
ns
Table 2-36
A54SX72A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions V
CCA
= 2.25 V, V
CCI
= 2.25 V, T
J
= 70°C)
Parameter
Description
–3 Speed
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.