Table 1-10 Power-Up Sequencing VCC" />
參數(shù)資料
型號(hào): A54SX08-VQG100I
廠商: Microsemi SoC
文件頁數(shù): 11/64頁
文件大?。?/td> 0K
描述: IC FPGA SX 12K GATES 100-VQFP
標(biāo)準(zhǔn)包裝: 90
系列: SX
LAB/CLB數(shù): 768
輸入/輸出數(shù): 81
門數(shù): 12000
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
SX Family FPGAs
v3.2
1-15
Power-Up Sequencing
Power-Down Sequencing
Table 1-10 Power-Up Sequencing
VCCA
VCCR
VCCI
Power-Up Sequence
Comments
A54SX08, A54SX16, A54SX32
3.3 V
5.0 V
3.3 V
5.0 V First
3.3 V Second
No possible damage to device
3.3 V First
5.0 V Second
Possible damage to device
A54SX16P
3.3 V
3.3 V Only
No possible damage to device
3.3 V
5.0 V
3.3 V
5.0 V First
3.3 V Second
No possible damage to device
3.3 V First
5.0 V Second
Possible damage to device
3.3 V
5.0 V
5.0 V First
3.3 V Second
No possible damage to device
3.3 V First
5.0 V Second
No possible damage to device
Note: No inputs should be driven (high or low) before completion of power-up.
Table 1-11 Power-Down Sequencing
VCCA
VCCR
VCCI
Power-Down Sequence
Comments
A54SX08, A54SX16, A54SX32
3.3 V
5.0 V
3.3 V
5.0 V First
3.3 V Second
Possible damage to device
3.3 V First
5.0 V Second
No possible damage to device
A54SX16P
3.3 V
3.3 V Only
No possible damage to device
3.3 V
5.0 V
3.3 V
5.0 V First
3.3 V Second
Possible damage to device
3.3 V First
5.0 V Second
No possible damage to device
3.3 V
5.0 V
5.0 V First
3.3 V Second
No possible damage to device
3.3 V First
5.0 V Second
No possible damage to device
Note: No inputs should be driven (high or low) after the beginning of the power-down sequence.
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