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參數(shù)資料
| 型號： | A54SX08-1PL208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | 54SX Family FPGAs |
| 中文描述： | 54SX家庭的FPGA |
| 文件頁數(shù)： | 34/57頁 |
| 文件大小： | 415K |
| 代理商： | A54SX08-1PL208 |
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5 4 S X F a m ily F P G A s
34
v3.1
P in De s c ript ion
C L K A /B
These pins are 3.3V/5.0V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior to
clocking the R-cells. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating. (For
A54SX72A, these clocks can be configured as bidirectional.)
C loc k A a nd B
G ND
LOW supply voltage.
G round
H C L K
De dic a te d (H a rd-w ire d)
A rra y C loc k
This pin is the 3.3V/5.0V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL, LVTTL,
3.3V PCI or 5.0V PCI specifications. Unused I/O pins are
automatically tristated by the Designer Series software.
Input/Output
NC
This pin is not connected to circuitry within the device.
No C onne c tion
P R A , I/O
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
P robe A
P R B , I/O
The Probe B pin is used to output data from any node within
the device. This diagnostic pin can be used in conjunction
with the Probe A pin to allow real-time diagnostic output of
any signal path within the device. The Probe B pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be permanently
disabled to protect programmed design confidentiality.
P robe B
T C K
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to
Table2 on page8
). This pin
functions as an I/O when the boundary scan state machine
reaches the “l(fā)ogic reset” state.
Te s t C loc k
T DI
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to
Table 2 on page 8
). This pin functions as an I/O
when the boundary scan state machine reaches the “l(fā)ogic
reset” state.
Te s t Da ta Input
T DO
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 2
on page 8
). This pin functions as an I/O when the boundary
scan state machine reaches the “l(fā)ogic reset” state.
Te s t Da ta Output
T MS
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO). In flexible mode when the TMS
pin is set LOW, the TCK, TDI, and TDO pins are boundary
scan pins (refer to
Table 2 on page 8
). Once the boundary
scan pins are in test mode, they will remain in that mode
until the internal boundary scan state machine reaches the
“l(fā)ogic reset” state. At this point, the boundary scan pins will
be released and will function as regular I/O pins. The “l(fā)ogic
reset” state is reached 5 TCK cycles after the TMS pin is set
HIGH. In dedicated test mode, TMS functions as specified in
the IEEE 1149.1 specifications.
Te s t Mode S e le c t
V
C C I
Supply voltage for I/Os. See
Table 1 on page 8
.
S upply V olta g e
V
C C A
Supply voltage for Array. See
Table 1 on page 8
.
S upply V olta g e
V
C C R
Supply voltage for input tolerance (required for internal
biasing) See
Table 1 on page 8
.
S upply V olta g e
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX08-1PL208I | 54SX Family FPGAs |
| A54SX08-1PL208M | 54SX Family FPGAs |
| A54SX08-1PL208PP | 54SX Family FPGAs |
| A54SX08-1PQ208 | 54SX Family FPGAs |
| A54SX08-1PQ208I | 54SX Family FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08-1PL208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-1PL208M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-1PL208PP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-1PL84 | 功能描述:IC FPGA SX 12K GATES 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A54SX08-1PL84I | 功能描述:IC FPGA SX 12K GATES 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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