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參數(shù)資料
| 型號： | A49LF040TL-33 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128 x 64 pixel format, LED Backlight available |
| 中文描述： | 4兆位的CMOS 3.3Volt只低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大小： | 570K |
| 代理商： | A49LF040TL-33 |
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Table 2: LPC Read Cycle
A49LF040
PRELIMINARY (August, 2004, Version 0.1)
6
AMIC Technology, Corp.
1. Field contents are valid on the rising edge of the present clock cycle.
LPC Single-Byte Read Waveforms
LCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
START
ADDRESS
TAR0
TAR1
SYNC
DATA
TAR0
TAR1
LFRAME#
LAD[3:0]
CYCTYPE +
DIR
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]
1
LAD[3:0]
Direction
Comments
1
START
0000
IN
LFRAME# must be active (low) for the part to respond. Only the last
start field (before LFRAME# transitioning high) should be recognized.
2
CYCTYPE
+ DIR
010X
IN
Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.
Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved.
3-10
ADDRESS
YYYY
IN
Address Phase for Memory Cycle. LPC protocol supports a 32-bit
address phase. YYYY is one nibble of the entire address. Addresses
are transferred most-significant nibble first. See Table 4 for address
bits definition and Table 5 for valid memory address range.
11
TAR0
1111
IN
then Float
In this clock cycle, the host has driven the bus to all 1s and then floats
the bus. This is the first part of the bus “turnaround cycle.”
12
TAR1
1111(float)
Float
then OUT
The A49LF040 takes control of the bus during this cycle.
13
SYNC
0000
OUT
The A49LF040 outputs the value 0000b indicating that data will be
available during the next clock cycle.
14
DATA
ZZZZ
OUT
This field is the least-significant nibble of the data byte.
15
DATA
ZZZZ
OUT
This field is the most-significant nibble of the data byte.
16
TAR0
1111
IN
then Float
In this clock, the host has driven the bus to all 1s and then floats the
bus. This is the first part of the bus “turnaround cycle.”
17
TAR1
1111(float)
Float
then OUT
The A49LF040 takes control of the bus during this cycle.
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