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參數(shù)資料
| 型號(hào)： | A49LF040A |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| 中文描述： | 4兆位的CMOS 3.3Volt只低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 622K |
| 代理商： | A49LF040A |
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A49LF040A
PRELIMINARY (March, 2006, Version 0.1)
13
AMIC Technology, Corp.
If this occurs, the system may possibly get an erroneous
result, i.e., valid data may appear to conflict with either I/O
7
or I/O
6
. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
In addition to I/O
6
and I/O
7
to detect the write status, a
pin is also available to detect the end of a Program or Erase
operation.
B
R/
is actively pulled low (V
IL
) during the internal
write cycles and is released to high (V
IH
) at the completion of
the cycle.
B
R/
Data
Polling (I/O
7
)
When the A49LF040A device is in the internal Program
operation, any attempt to read I/O
7
will produce the
complement of the true data. Once the Program operation is
completed, I/O
7
will produce true data. Note that even though
I/O
7
may have valid data immediately following the
completion of an internal Write operation, the remaining data
outputs may still be invalid: valid data on the entire data bus
will appear in subsequent successive Read cycles after an
interval of 1 μs. During internal Erase operation, any attempt
to read I/O
7
will produce a ‘0’. Once the internal Erase
operation is completed, I/O
7
will produce a ‘1’. The
Data
Polling is valid after the rising edge of fourth
WE
pulse for
Program operation. For Block- or Chip-Erase, the
Data
Polling is valid after the rising edge of sixth
WE
pulse. See
Figure 12 for
Data
Polling timing diagram. Proper status will
not be given using
Data
Polling if the address is in the
invalid range.
Toggle Bit (I/O
6
)
During the internal Program or Erase operation, any
consecutive attempts to read I/O
6
will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth
WE
pulse
for Program operation. For Block- or Chip-Erase, the Toggle
Bit is valid after the rising edge of sixth
WE
pulse. See
Figure 13 for Toggle Bit timing diagram.
Data Protection
The A49LF040A device provides both hardware and
software features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A
WE
pulse of less than 5 ns will
not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE low,
WE
high will inhibit the
Write operation. This prevents inadvertent writes during
power-up or power-down.
Software Data Protection (SDP)
The A49LF040A provides the JEDEC approved Software
Data Protection scheme for all data alteration operation, i.e.,
Program and Erase. Any Program operation requires the
inclusion of a series of three-byte sequences. The three-byte
load sequence is used to initiate the Program operation,
providing
optimal
protection
operations, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of a six-byte load
sequence. The A49LF040A device is shipped with the
Software Data Protection permanently enabled. See Table
11 for the specific software command codes. During SDP
command sequence, invalid commands will abort the device
to Read mode, within T
RC
.
from
inadvertent
Write
Electrical Specifications
The AC and DC specifications for the LPC Interface signals
(LAD[3:0], LCLK, LFRAME , and RST ) as defined in Section
4.2.2 of the
PCI Local Bus Specification, Rev. 2.1
. Refer to
Table 12 for the DC voltage and current specifications. Refer
to the specifications on Table 12 to Table 22 for Clock,
Read/Write, and Reset operations.
Product Identification
The product identification mode identifies the Manufacturer
ID, Continuation ID, and Device ID of the A49LF040A. See
Table 10 for detail information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A49LF040ATL-33 | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040ATL-33F | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040ATX-33 | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040ATX-33F | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040TX-33 | 240 x 128 pixel format, LED or EL Backlight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A49LF040ATL-33 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040ATL-33F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040ATX-33 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040ATX-33F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
| A49LF040TL-33 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory |
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