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參數(shù)資料
| 型號： | A45L9332AF-8 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 32 Bit X 2 Banks Synchronous Graphic RAM |
| 中文描述： | 256 × 32位× 2銀行同步圖形內(nèi)存 |
| 文件頁數(shù)： | 12/55頁 |
| 文件大小： | 1255K |
| 代理商： | A45L9332AF-8 |
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A45L9332A Series
PRELIMINARY
(October, 2001, Version 0.1)
11
AMIC Technology, Inc.
Simplified Truth Table
4. A10 : Bank select address.
If “Low” at read, (block) write, Row active and precharge, bank A is selected.
If “High” at read, (block) write, Row active and precharge, bank B is selected.
If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.
5. It is determined at Row active cycle.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit = I/O mask
(Block) Write with write per bit mode = Masked (Block ) Write
6. During burst read or write with auto precharge, new read/ (block) write command cannot be issued.
Another bank read/(block) write command can be issued at t
PR
after the end of burst.
7. Burst stop command is valid only t full page burst length.
8. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
9. Graphic features added to SDRAM’s original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ’s.
SGRAM vs SDRAM
Function
MRS
Bank Active
Write
DSF
L
H
L
H
L
H
SGRAM
Function
MRS
SMRS
Bank Active
with
Write per bit
Disable
Bank Active
with
Write per bit
Enable
Normal
Write
Block
Write
IF DSF is low, SGRAM functionality is identical to SDRAM functionality.
SGRAM can be used as an unified memory by the appropriate DSF control
→
SDRAM = Graphic Memory + main Memory
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