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參數(shù)資料
| 型號： | A45L9332AF-7 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 32 Bit X 2 Banks Synchronous Graphic RAM |
| 中文描述： | 256 × 32位× 2銀行同步圖形內(nèi)存 |
| 文件頁數(shù)： | 5/55頁 |
| 文件大?。?/td> | 1255K |
| 代理商： | A45L9332AF-7 |
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A45L9332A Series
PRELIMINARY
(October, 2001, Version 0.1)
4
AMIC Technology, Inc.
Pin Descriptions
Symbol
Name
Description
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t ss prior to new command.
Disable input buffers for power down in standby.
A0~A9
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA9, Column address: CA0~CA7
A10(BA)
Bank Select Address
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
DQMi
Data Input/Output Mask
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte Masking)
DQi
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
DSF
Define Special Function
Enables write per bit, block write and special mode register set.
VDD/VSS
Power Supply/Ground
Power Supply: +3.3V
±
0.3V/Ground
VDDQ/VS
SQ
Data Output
Power/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
NC
No Connection
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