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  • 參數(shù)資料
    型號(hào): A43L8316V
    廠商: AMIC Technology Corporation
    英文描述: 128K X 16 Bit X 2 Banks Synchronous DRAM
    中文描述: 128K的× 16位× 2銀行同步DRAM
    文件頁數(shù): 4/45頁
    文件大?。?/td> 1395K
    代理商: A43L8316V
    A43L8316
    Preliminary (April, 2000, Version 1.0)
    3
    AMIC Technology, Inc.
    Pin Descriptions
    Symbol
    Name
    Description
    CLK
    System Clock
    Active on the positive going edge to sample all inputs.
    CS
    Chip Select
    Disables or Enables device operation by masking or enabling all inputs except
    CLK, CKE and L(U)DQM
    CKE
    Clock Enable
    Masks system clock to freeze operation from the next clock cycle.
    CKE should be enabled at least one clock + tss prior to new command.
    Disable input buffers for power down in standby.
    A0~A8/AP
    Address
    Row / Column addresses are multiplexed on the same pins.
    Row address : RA0~RA8, Column address: CA0~CA7
    BA
    Bank Select Address
    Selects bank to be activated during row address latch time.
    Selects band for read/write during column address latch time.
    RAS
    Row Address Strobe
    Latches row addresses on the positive going edge of the CLK with
    RAS
    low.
    Enables row access & precharge.
    CAS
    Column Address
    Strobe
    Latches column addresses on the positive going edge of the CLK with CAS low.
    Enables column access.
    WE
    Write Enable
    Enables write operation and Row precharge.
    L(U)DQM
    Data Input/Output
    Mask
    Makes data output Hi-Z, t SHZ after the clock and masks the output.
    Blocks data input when L(U)DQM active.
    DQ
    0-15
    Data Input/Output
    Data inputs/outputs are multiplexed on the same pins.
    VDD/VSS
    Power
    Supply/Ground
    Power Supply: +3.3V
    ±
    0.3V/Ground
    VDDQ/VSSQ
    Data Output
    Power/Ground
    Provide isolated Power/Ground to DQs for improved noise immunity.
    NC/RFU
    No Connection
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