- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375140 > A43L1632 (AMIC Technology Corporation) 512K X 32 Bit X 4 Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | A43L1632 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 32 Bit X 4 Banks Synchronous DRAM |
| 中文描述： | 為512k × 32位× 4個銀行同步DRAM |
| 文件頁數(shù)： | 16/43頁 |
| 文件大?。?/td> | 1076K |
| 代理商： | A43L1632 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
A43L1632
PRELIMINARY (December, 2004, Version 0.0)
15
AMIC Technology, Corp.
All Banks Precharge
All banks can be precharged at the same time by using
Precharge all command. Asserting low on
CS
,
RAS
and
WE
with high on A10/AP after both banks have satisfied
t
RAS
(min) requirement, performs precharge on all banks. At
the end of tRP after performing precharge all, all banks are in
idle state.
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on
CS
,
RAS
and
CAS
with high on CKE and
WE
. The auto refresh command can only be asserted with
all banks being in idle state and the device is not in power
down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified
by “t
RC
(min)”. The minimum number of clock cycles required
can be calculated by dividing “t
RC
” with clock cycle time and
then rounding up to the next higher integer. The auto refresh
command must be followed by NOP’s until the auto refresh
operation is completed. All banks will be in the idle state at
the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 4096 auto refresh
cycles once in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on
CS
,
RAS
,
CAS
and CKE with high on
WE
. Once the self refresh mode is entered, only CKE state
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “t
RC
” before the SDRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 4096 auto refresh cycles immediately after exiting self
refresh.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A43L1632V-6 | 512K X 32 Bit X 4 Banks Synchronous DRAM |
| A43L1632V-7 | 512K X 32 Bit X 4 Banks Synchronous DRAM |
| A43L2616AG-6F | 1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43L2616A | 1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43L2616AG-6 | 1M X 16 Bit X 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43L1632G-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43L1632G-95I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43L1632V-6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 4 Banks Synchronous DRAM |
| A43L1632V-7 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 4 Banks Synchronous DRAM |
| A43L1632V-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。