參數(shù)資料
型號: A43L0616BV-7UF
廠商: AMIC Technology Corporation
英文描述: 512K X 16 Bit X 2 Banks Synchronous DRAM
中文描述: 為512k × 16位× 2銀行同步DRAM
文件頁數(shù): 9/45頁
文件大?。?/td> 1275K
代理商: A43L0616BV-7UF
A43L0616B
PRELIMINARY
(May, 2005, Version 0.0)
8
AMIC Technology, Corp.
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version
Symbol
Parameter
CAS
Latency
-6
-7
Unit
Note
t
RRD(min)
Row active to row active delay
12
14
ns
1
t
RCD(min)
RAS to
CAS
delay
18
20
ns
1
t
RP(min)
Row precharge time
18
20
ns
1
t
RAS(min)
42
42
ns
1
t
RAS(max)
Row active time
100
μ
s
t
RC(min)
Row cycle time
60
63
ns
1
t
CDL(min)
Last data in new col. Address delay
1
CLK
2
t
RDL(min)
Last data in row precharge
2
2
CLK
2
t
BDL(min)
Last data in to burst stop
1
CLK
2
t
CCD(min)
Col. Address to col. Address delay
1
CLK
3
2
CLK
4
Number of valid output data
2
1
CLK
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
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