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參數(shù)資料
| 型號： | A43L0616BV-7U |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 16 Bit X 2 Banks Synchronous DRAM |
| 中文描述： | 為512k × 16位× 2銀行同步DRAM |
| 文件頁數(shù)： | 11/45頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | A43L0616BV-7U |
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A43L0616B
PRELIMINARY
(May, 2005, Version 0.0)
10
AMIC Technology, Corp.
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
BA
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 1)
(Note 2)
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
Reserved
0
1
0
0
1
-
1
Interleave
0
0
1
2
Reserved
1
0
0
1
0
2
0
1
0
4
4
1
1
Vendor
Use
Only
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
A9
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
(Note 3)
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200
μ
s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note :
1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
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相關代理商/技術參數(shù) |
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| A43L0616BV-7UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 16 Bit X 2 Banks Synchronous DRAM |
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| A43L0616V-7I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
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