參數(shù)資料
型號(hào)： A42MX36
廠商： Electronic Theatre Controls, Inc.
英文描述： Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 42/123頁
文件大?。?/td> 854K
代理商： A42MX36
40MX and 42MX FPGA Families
1-36
v6.0
Timing Characteristics
Table 28
A40MX02 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CC
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Logic Module Propagation Delays
t
PD1
Single Module
1.2
1.4
1.6
1.9
2.7
ns
t
PD2
Dual-Module Macros
2.7
3.1
3.5
4.1
5.7
ns
t
CO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
t
GO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
t
RS
Logic Module Predicted Routing Delays
1
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
t
RD1
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.8
ns
t
RD2
FO=2 Routing Delay
1.8
2.1
2.4
2.8
3.9
ns
t
RD3
FO=3 Routing Delay
2.3
2.7
3.0
3.6
5.0
ns
t
RD4
FO=4 Routing Delay
2.9
3.3
3.7
4.4
6.1
ns
t
RD8
Logic Module Sequential Timing
2
FO=8 Routing Delay
4.9
5.7
6.5
7.6
10.6
ns
t
SUD
t
HD3
Flip-Flop (Latch) Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
t
HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
WCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
t
WASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
t
A
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
f
MAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
181
168
154
134
80
MHz
Input Module Propagation Delays
t
INYH
Pad-to-Y HIGH
0.7
0.8
0.9
1.1
1.5
ns
t
INYL
Pad-to-Y LOW
0.6
0.7
0.8
1.0
1.3
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
相關(guān)PDF資料
PDF描述
A42MX36-1VQ100I Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
A42MX36-1VQ100M Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
A42MX36-2BG100M 40MX and 42MX FPGA Families
A42MX36-2VQ100M 40MX and 42MX FPGA Families
A42MX36-3BG100A Hex Inverters 14-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-1BG272 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX36-1BG272I 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-1BG272M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 54K Gates 1184 Cells 90MHz/151MHz 0.45um Technology 3.3V/5V 272-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 90MHZ/151MHZ 0.45UM 3.3V/5V 272BGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA
A42MX36-1BGG272 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX36-1BGG272I 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
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