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    參數(shù)資料
    

    


    


    
型號(hào)：
A42MX36-FPQ240

    

    
廠商：
Microsemi SoC

    

    
文件頁數(shù)：
129/142頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA MX SGL CHIP 54K 240-PQFP

    

    
標(biāo)準(zhǔn)包裝：
24

    

    
系列：
MX

    

    
RAM 位總計(jì)：
2560
    		

    

    
輸入/輸出數(shù)：
202
    		

    

    
門數(shù)：
54000
    		

    

    
電源電壓：
3 V ~ 3.6 V，4.75 V ~ 5.25 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 70°C
    		

    

    
封裝/外殼：
240-BFQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
240-PQFP（32x32）
    		

    

    

    

	
    
    
    

    
    
	
    40MX and 42MX FPGA Families
    Re vi s i on 11
    1 - 83
    Pin Descriptions
    CLK/A/B, I/O
    Global Clock
    Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX
    devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an
    I/O.
    DCLK, I/O
    Diagnostic Clock
    Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.
    This pin functions as an I/O when the MODE pin is LOW.
    GND
    Ground
    Input LOW supply voltage.
    I/O
    Input/Output
    Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and
    CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 1-40.
    In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all
    dual-purpose pins when configured as I/Os as well.
    LP
    Low Power Mode
    Controls the low power mode of all 42MX devices. The device is placed in the low power mode by
    connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned
    OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW.
    The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume
    normal operation in 200 s after the LP pin is driven to a logic LOW.
    MODE
    Mode
    Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to
    provide verification capability. The MODE pin should be terminated to GND through a 10k
    Ω resistor so
    that the MODE pin can be pulled HIGH when required.
    NC
    No Connection
    This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
    left floating with no effect on the operation of the device.
    PRA, I/O
    PRB, I/O
    Probe A/B
    The Probe pin is used to output data from any user-defined design node within the device. Each
    diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of
    any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has
    been completed. The pin's probe capabilities can be permanently disabled to protect programmed design
    confidentiality. The Probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O
    when the MODE pin is LOW.
    QCLKA/B/C/D, I/O
    Quadrant Clock
    Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can
    function as user I/Os.
    Table 1-40  Configuration of Unused I/Os
    Device
    Configuration
    A40MX02, A40MX04
    Pulled LOW
    A42MX09, A42MX16
    Pulled LOW
    A42MX24, A42MX36
    Tristated
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
A42MX36-FPQG208
功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）

    

    
A42MX36-FPQG240
功能描述:IC FPGA MX SGL CHIP 54K 240-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）

    

    
A42MX36-PQ208
功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）

    

    
A42MX36-PQ208A
功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）

    

    
A42MX36-PQ208I
功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）

    

    
    
    
    
	
    	
    
    
     
     
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