參數(shù)資料
型號： A42MX36-CQ208B
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場可編程門陣列（FPGA）
文件頁數(shù)： 10/116頁
文件大?。?/td> 3110K
代理商： A42MX36-CQ208B
40MX and 42MX FPGA Families
10
v5.0
Test Circuitry
All devices contain Actel
’
s ActionProbe test circuitry which
test and debug a design once it is programmed into a device.
Once a device has been programmed, the ActionProbe test
circuitry allows the designer to probe any internal node
during device operation to aid in debugging a design. In
addition, 42MX devices contain IEEE Standard 1149.1
boundary scan test circuitry.
IEEE Standard 1149.1 Boundary Scan Testing (BST)
IEEE Standard 1149.1 defines a four-pin Test Access Port
(TAP) interface for testing integrated circuits in a system.
The 42MX family provides five BST pins: Test Data In (TDI),
Test Data Out (TDO), Test Clock (TCK), and Test Mode
Select Test Reset (TRST) (42MX24A only). Devices are
configured in a test
“
chain
”
where BST data can be
transmitted serially between devices via TDO-to-TDI
interconnections. The TMS and TCK signals are shared
among all devices in the test chain so that all components
operate in the same state.
The 42MX family implements a subset of the IEEE Standard
1149.1 BST instruction in addition to a private instruction,
which allows the use of Actel
’
s ActionProbe facility with
BST. Refer to the IEEE Standard 1149.1 specification for
detailed information regarding BST.
Boundary Scan Circuitry
The 42MX boundary scan circuitry consists of a Test Access
Port (TAP) controller, test instruction register, a JPROBE
register, a bypass register, and a boundary scan register.
Figure 11 on page 11
shows a block diagram of the 42MX
boundary scan circuitry.
Figure 10
Quadrant Clock Network
Quad
Clock
Module
QCLKA
QCLKB
*QCLK1IN
S0 S1
QCLK1
Quad
Clock
Module
*QCLK2IN
S0 S1
QCLK2
Quad
Clock
Module
QCLKC
QCLKD
*QCLK3IN
S0
S1
QCLK3
Quad
Clock
Module
*QCLK4IN
S0
S1
QCLK4
*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
相關(guān)PDF資料
PDF描述
A42MX36-CQ208M Field Programmable Gate Array (FPGA)
A42MX36-CQ256 Field Programmable Gate Array (FPGA)
A42MX36-CQ256B Field Programmable Gate Array (FPGA)
A42MX36-CQ256M Field Programmable Gate Array (FPGA)
A42MX36-FBG272 Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-CQ208M 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 208CQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 176 I/O 208CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP
A42MX36-CQ256 功能描述:IC FPGA MX SGL CHIP 54K 256-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-CQ256B 功能描述:IC FPGA MX SGL CHIP 54K 256-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-CQ256M 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 256CQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 256CQFP
A42MX36-FBG272 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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