參數(shù)資料
型號(hào)： A42MX36-2CQ208B
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁數(shù)： 5/116頁
文件大?。?/td> 3110K
代理商： A42MX36-2CQ208B
v5.0
5
40MX and 42MX FPGA Families
Power Requirements
40MX
The 40MX FPGAs will operate in 5.0V-only systems or
3.3V-only systems.
V
CC
Input
Output
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
42MX
The 42MX FPGAs will operate in 5.0V-only systems,
3.3V-only systems, or mixed 5.0V/3.3V systems.
V
CCA
V
CCI
Input
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
5.0V
3.3V
3.3V, 5.0V
Output
5.0V
3.3V
3.3V
Mixed Voltage Power Up and Power
Down
When powering up the device in the mixed voltage mode
(V
CCA
= 5.0V and V
CCI
= 3.3V), V
CCA
must be greater than or
equal to V
CCI
throughout the power-up sequence. If V
CCI
is
0.5V greater than V
CCA
when both are above 1.5V, then the
I/Os
’
input protection junction on the I/Os will be forward
biased, causing them to draw large amounts of current.
When V
CCA
and V
CCI
are in the 1.5V to 2.0V region and V
CCI
is greater than V
CCA
, all I/Os would momentarily behave as
outputs that are in a logical high state, and I
CC
rises to high
levels. For power down, any sequence with V
CCA
and V
CCI
can be implemented.
Low Power Mode
The 42MX devices have a power-saving feature enabled by a
special Low Power pin (LP). In this mode, the device
consumes very minimal power, with standby current as low
as 15μA (see
“
Electrical Specifications
”
on page 13
and
14
).
All μ I/Os are tristated, all input buffers are turned off, and
the core of the device is turned off. Since the core is turned
off, the state of the registers and the contents of the SRAM
are lost. The device enters low power mode 800ns after the
LP pin is set High. It will resume normal operation 200μs
after the LP pin is driven to a logic Low.
MX Architectural Overview
The 40MX and 42MX devices are composed of fine-grained
building blocks that enable fast, efficient logic designs. All
devices within these families are composed of logic
modules, I/O modules, routing resources, and clock
networks, which are the building blocks for designing fast
logic designs. In addition, the A42MX36 device contains
embedded dual-port SRAM and wide decode modules. The
dual-port SRAM modules are optimized for high-speed
datapath functions such as FIFOs, LIFOs, and scratchpad
memory. The
“
Product Profile
”
on page 1
lists the specific
logic resources contained within each device.
Logic Modules
The 40MX logic module is an eight-input, one-output logic
circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources (
Figure 1
).
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two, three,
or four inputs. Each function may have many versions with
different combinations of active LOW inputs. The logic
module can also implement a variety of D-latches,
exclusivity functions, AND-ORs, and OR-ANDs. No dedicated
hard-wired latches or flip-flops are required in the array,
since latches and flip-flops can be constructed from logic
modules wherever needed in the application.
Figure 1
40MX Logic Module
相關(guān)PDF資料
PDF描述
A42MX36-2CQ208M Field Programmable Gate Array (FPGA)
A42MX36-2CQ256 Field Programmable Gate Array (FPGA)
A42MX36-BG272I Field Programmable Gate Array (FPGA)
A42MX36-BG272M Field Programmable Gate Array (FPGA)
A42MX36-CQ208 Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-2PQ208 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX36-2PQ208I 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-2PQ240 功能描述:IC FPGA MX SGL CHIP 54K 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX36-2PQ240I 功能描述:IC FPGA MX SGL CHIP 54K 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-2PQG208 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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