參數(shù)資料
型號： A42MX24-FVQ100M
廠商： Electronic Theatre Controls, Inc.
英文描述： Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 28/123頁
文件大?。?/td> 854K
代理商： A42MX24-FVQ100M
40MX and 42MX FPGA Families
1-22
v6.0
Junction Temperature (T
J
)
The temperature variable in the Designer software refers
to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature.
EQ 1-1
,
shown below, can be used to calculate junction
temperature.
EQ 1-1
Junction Temperature =
T + T
a
(1)
Where:
T
a
= Ambient Temperature
T = Temperature gradient between junction (silicon)
and ambient
T =
θ
ja
* P(2)
P = Power
θ
ja
= Junction to ambient of package.
θ
ja
numbers are
located in the Package Thermal Characteristics table
below.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is
θ
jc
,
and the junction-to-ambient air characteristic is
θ
ja
. The
thermal characteristics for
θ
ja
are shown with two
different air flow rates.
The maximum junction temperature is 150
°
C.
Maximum power dissipation for commercial- and
industrial-grade devices is a function of
θ
ja
.
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 176-pin package at
commercial temperature and still air is as follow:
The maximum power dissipation for military-grade devices is a function of
θ
jc
. A sample calculation of the absolute
maximum power dissipation allowed for CQFP 208-pin package at military temperature and still air is as follows:
---------------------------------------------------------------------------------------------------------------------------------
°
C)
Max. ambient temp. (
°
C)
–
θ
jc
(
°
C/W)
Table 21
Package Thermal Characteristics
Plastic Packages
Pin Count
θ
jc
θ
ja
Units
Still Air
1.0 m/s
200 ft/min.
2.5 m/s
500 ft/min.
Plastic Quad Flat Pack
100
12.0
27.8
23.4
21.2
°C/W
Plastic Quad Flat Pack
160
10.0
26.2
22.8
21.1
°C/W
Plastic Quad Flat Pack
208
8.0
26.1
22.5
20.8
°C/W
Plastic Quad Flat Pack
240
8.5
25.6
22.3
20.8
°C/W
Plastic Leaded Chip Carrier
44
16.0
20.0
24.5
22.0
°C/W
Plastic Leaded Chip Carrier
68
13.0
25.0
21.0
19.4
°C/W
Plastic Leaded Chip Carrier
84
12.0
22.5
18.9
17.6
°C/W
Thin Plastic Quad Flat Pack
176
11.0
24.7
19.9
18.0
°C/W
Very Thin Plastic Quad Flat Pack
80
12.0
38.2
31.9
29.4
°C/W
Very Thin Plastic Quad Flat Pack
100
10.0
35.3
29.4
27.1
°C/W
Plastic Ball Grid Array
272
3.0
18.3
14.9
13.9
°C/W
Ceramic Packages
Ceramic Quad Flat Pack
208
2.0
22.0
19.8
18.0
°C/W
Ceramic Quad Flat Pack
256
2.0
20.0
16.5
15.0
°C/W
Maximum Power Allowed
°
C)
Max. junction temp. (
Max. ambient temp. (
°
C)
θ
ja
(
°
C/W)
–
°
C
28
°
C/W
70
°
C
–
150
2.86W
=
=
=
Maximum Power Allowed
°
C
150
125
°
C
–
6.3
°
C/W
3.97W
=
=
=
相關PDF資料
PDF描述
A42MX36 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
A42MX36-1VQ100I Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
A42MX36-1VQ100M Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
A42MX36-2BG100M 40MX and 42MX FPGA Families
A42MX36-2VQ100M 40MX and 42MX FPGA Families
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