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  • 參數(shù)資料
    型號: A42MX24-FVQ100
    廠商: Electronic Theatre Controls, Inc.
    英文描述: Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SSOP -40 to 85
    中文描述: 40MX和42MX FPGA系列
    文件頁數(shù): 29/123頁
    文件大?。?/td> 854K
    代理商: A42MX24-FVQ100
    40MX and 42MX FPGA Families
    v6.0
    1-23
    Timing Models
    Note:
    Figure 1-17
    40MX Timing Model*
    * Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.
    Notes:
    *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.
    Input module predicted routing delay.
    Figure 1-18
    42MX Timing Model*
    Output Delay
    Input Delay
    Logic Module
    Internal Delays
    tDLH=3.32 ns
    tENHZ=7.92 ns
    tRD1=1.28 ns
    tRD2=1.80 ns
    tRD4=2.33 ns
    tRD8=4.93 ns
    I/O Module
    tPD=1.24 ns
    tCO=1.24 ns
    tIRD1=2.09 ns
    tIRD4=3.64 ns
    tIRD8=5.73 ns
    tINYL=0.62 ns tIRD2=2.59 ns
    I/O Module
    FMAX=180 MHz
    tCKH=4.55 ns
    FO=128
    Array
    Clock
    Predicted
    Routing
    Delays
    Array
    Clocks
    Combin
    -atorial
    Logic
    include
    D
    Q
    FO = 32
    Output Delays
    Internal Delays
    Input Delays
    I/O Module
    D
    Q
    Combinatorial
    Logic Module
    Sequential
    Logic Module
    I/O Module
    I/O Module
    D
    Q
    Predicted
    Routing
    Delays
    G
    G
    tRD1=0.7 ns
    tRD2=1.9 ns
    tRD4=1.4 ns
    tRD8=2.3 ns
    tOUTH=0.00 ns
    tOUTSU=0.3 ns
    tGLH=2.6 ns
    tDLH=2.5 ns
    tDLH=2.5 ns
    tENHZ=4.9 ns
    tRD1=0.70 ns
    tLCO=5.2 ns (light loads, pad-to-pad)
    tCO=1.3 ns
    tSUD=0.3 ns
    tHD=0.00 ns
    tPD=1.2 ns
    tIRD1=2.0 ns
    tINYL=0.8 ns
    tINH=0.0 ns
    tINSU=0.3 ns
    tINGL=1.3 ns
    FMAX=296 MHz
    tCKH=2.70 ns
    相關(guān)PDF資料
    PDF描述
    A42MX24-FVQ100A 40MX and 42MX FPGA Families
    A42MX24-FVQ100B Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
    A42MX24-FVQ100ES Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
    A42MX24-FVQ100I Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
    A42MX24-FVQ100M Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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