參數(shù)資料
型號： A42MX24-FTQ100I
廠商： Electronic Theatre Controls, Inc.
英文描述： Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 75/123頁
文件大?。?/td> 854K
代理商： A42MX24-FTQ100I
40MX and 42MX FPGA Families
v6.0
1-69
Table 38
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Logic Module Combinatorial Functions
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
PD
t
PDD
Logic Module Predicted Routing Delays
2
Internal Array Module Delay
1.3
1.5
1.7
2.0
2.7
ns
Internal Decode Module Delay
1.6
1.8
2.0
2.4
3.3
ns
t
RD1
t
RD2
t
RD3
t
RD4
t
RD5
t
RDD
Logic Module Sequential Timing
3, 4
FO=1 Routing Delay
0.9
1.0
1.2
1.4
2.0
ns
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.4
ns
FO=4 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
FO=8 Routing Delay
3.3
3.7
4.2
4.9
6.9
ns
Decode-to-Output Routing Delay
0.3
0.4
0.4
0.5
0.7
ns
t
CO
t
GO
t
SUD
t
HD
t
RO
t
SUENA
t
HENA
t
WCLKA
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.7
ns
Flip-Flop (Latch) Set-Up Time
0.3
0.3
0.4
0.5
0.7
ns
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Reset-to-Output
1.6
1.7
2.0
2.3
3.2
ns
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4
4.8
5.5
6.4
9.0
ns
Synchronous SRAM Operations
t
RC
t
WC
t
RCKHL
t
RCO
t
ADSU
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Read Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
Write Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
Clock HIGH/LOW Time
3.4
3.8
4.3
5.0
7.0
ns
Data Valid After Clock HIGH/LOW
3.4
3.8
4.3
5.0
7.0
ns
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
相關(guān)PDF資料
PDF描述
A42MX24-FTQ100M Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SSOP -40 to 85
A42MX36-FCQ100M 40MX and 42MX FPGA Families
A42MX36-FPL100 40MX and 42MX FPGA Families
A42MX36-FPL100A 40MX and 42MX FPGA Families
A42MX36-FPL100B 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX24-FTQ176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX24-FTQG176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX24-PL84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX24-PL84I 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-PL84M 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 84PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 72 I/O 84PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*