參數(shù)資料
型號： A42MX24-3TQ100M
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 65/123頁
文件大小： 854K
代理商： A42MX24-3TQ100M
40MX and 42MX FPGA Families
v6.0
1-59
Table 35
A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Logic Module Propagation Delays
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
PD1
t
CO
t
GO
t
RS
Logic Module Predicted Routing Delays
2
Single Module
1.9
2.1
2.4
2.8
4.0
ns
Sequential Clock-to-Q
2.0
2.2
2.5
3.0
4.2
ns
Latch G-to-Q
1.9
2.1
2.4
2.8
4.0
ns
Flip-Flop (Latch) Reset-to-Q
2.2
2.4
2.8
3.3
4.6
ns
t
RD1
t
RD2
t
RD3
t
RD4
t
RD8
Logic Module Sequential Timing
3, 4
FO=1 Routing Delay
1.1
1.2
1.4
1.6
2.3
ns
FO=2 Routing Delay
1.5
1.6
1.8
2.1
3.0
ns
FO=3 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
FO=4 Routing Delay
2.2
2.4
2.7
3.2
4.5
ns
FO=8 Routing Delay
3.6
4.0
4.5
5.3
7.5
ns
t
SUD
t
HD
t
SUENA
t
HENA
t
WCLKA
Flip-Flop (Latch) Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Clock Active
Pulse Width
4.8
5.3
6.0
7.1
9.9
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.2
6.9
7.9
9.2
12.9
ns
t
A
t
INH
t
INSU
t
OUTH
t
OUTSU
f
MAX
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Flip-Flop Clock Input Period
9.5
10.6
12.0
14.1
19.8
ns
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
Input Buffer Latch Set-Up
0.7
0.8
0.9
1.01
1.4
ns
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
Output Buffer Latch Set-Up
0.7
0.8
0.89
1.01
1.4
ns
Flip-Flop (Latch) Clock Frequency
129
117
108
94
56
MHz
相關PDF資料
PDF描述
A42MX24-3VQ100ES Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
A42MX24-3VQ100I Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
A42MX24-3VQ100M Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
A42MX24-FBG100 Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
A42MX24-FVQ100 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SSOP -40 to 85
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